Datasheet

LTC2934
9
2934f
TYPICAL APPLICATIONS
Battery Monitor with Interface to Low Voltage Logic
Alkaline Cell Stack Voltage Monitor
Coin Cell Voltage Monitor
1.18M
1μF
590k
100k
324k
100k
100k
V
CC
V
DD
μP
POWER FAIL FALLING THRESHOLD = 3.192V
RESET FALLING THRESHOLD = 1.696V
*OPTIONAL RESISTOR FOR ADDED ESD PROTECTION
2934 TA02
698k
100k
NMI
RST
RT
ADJ
Li-Ion
0.1μF
SHDN
IN OUT
3μA LDO
1.8V
ADJ
PFO
PB1
RST
PFI
MR
LTC2934-1
LT3009
R
ESD
*
10k
GND
GND
+
V
CC
2934 TA03
RT
ADJ
1.5V
0.1μF
PFI
LTC2934-2
GND
+
1.5V
+
1.5V
+
RST
PFO
MR
POWER FAIL THRESHOLD = 2.628V
RESET THRESHOLD = 2.428V
845k
12.7k
LOW BATTERY
SYSTEM RESET
154k
APPLICATIONS INFORMATION
Manual Reset Input
When V
CC
is above its reset threshold, and the manual
reset input (MR) is pulled low, the RST output is forced
low. RST remains low for the selected reset timeout
period after the manual reset input is released and pulled
high. The manual reset input is pulled up internally through
900k to V
CC
. If external leakage currents have the ability
to pull down the manual reset input below its logic thresh-
old, a lower value pull-up resistor, placed between V
CC
and
MR will fi x the problem.
Input MR is often pulled down through a pushbutton
switch requiring human contact. If extended ESD toler-
ance is required, series resistance between the switch and
the input is recommended. For most applications a 10k
resistor provides suffi cient current limiting.
Selecting the Reset Timeout Period
Use the RT input to select between two fi xed reset timeout
periods. Connect RT to ground for a 15ms timeout. Connect
RT to V
CC
for a 200ms timeout. The reset timeout period
occurs after the ADJ input is driven above threshold. After
the reset timeout period, the RST output is allowed to pull
up to a high state.
V
CC
2934 TA04
RT
ADJ
0.1μF
PFI
LTC2934-2
GND
CR2032
+
RST
PFO
MR
POWER FAIL THRESHOLD = 2.727V
RESET THRESHOLD = 2.553V
845k
10k
147k
LOW BATTERY
SYSTEM RESET