Datasheet

LTC2928
26
2928f
2) Sequence-Up Phase
Start the sequence-up phase by transitioning the ON input
above 1V. At this point, the LTC2928 senses the sequence
position resistors on inputs RT1 through RT4. The sequence
timer is operating and the CAS pin pulls low at the start
of each time position. The CMP outputs are low during
sequencing unless a fault has occurred.
Protect shutdown inputs on regulators that are sensitive
to high voltage. In this application, the FPGA regulators
have their shutdown inputs connected to the 3.3V supply
through a 10k resistor, thereby limiting the pull-up voltage
on the shutdown inputs (the EN outputs alone may attempt
to pull-up as high as 9.3V (V
CC
+ 6V).
DONE pulls low when all time positions are clocked through
(CAS has completed pulling low 8 times). The compara-
tor outputs become active and are allowed to pull high if
the supply monitor inputs are above their under-voltage
threshold.
The RST output pulls high after all the supplies have
remained above their undervoltage threshold for ap-
proximately 190ms. After RST is allowed to pull high, the
LTC2928 enters its supply-monitor phase. The LTC2928
RST pin pulls up to 3.3V. The schottky diode SD1 and
resistor RP1 limit the pull-up voltage at the FPGA reset pin.
3) Supply Monitor Phase
During the supply-monitor phase, if any of the four sup-
plies drops below its selected threshold, RST pulls low.
Since this application considers an under-voltage condition
during the supply-monitor phase to be a reset fault, F LT
pulls low. All enable outputs pull low and the pass transis-
tors shut off. Because of the fault condition, the LTC2928
is prevented from re-sequencing until all supplies drop
below their sequence-down threshold, and the ON input
is below 0.97V.
4) Sequence-Down Phase
Begin the sequence-down phase by pulling the ON input
below 0.97V. RST and all CMP outputs pull low as soon as
the sequence-down command is detected. Beginning with
supplies in time position 8, the supplies are sequenced-
down reverse of the order in which they came up. At the
end of the sequence-down phase, DONE pulls high (CAS
has completed pulling low 8 times).
Overvoltage Indication
If any positive supply monitor input exceeds its overvoltage
threshold at any time, OV pulls low. OV returns high once
all positive supplies are below their overvoltage threshold
for a period equal to the RST delay time. To shutdown all
supplies upon overvoltage, tie the OV output to F LT .
Overvoltage Threshold Adjustment
Use the OVA input to set the overvoltage threshold for
all positive supplies. Leave the OVA input open to set the
OV threshold at the supply monitor inputs to 32% above
the undervoltage threshold (V
OVA
= 0.660V). Ground the
OVA input to set the OV threshold to 12% above the un-
dervolatge threshold (V
OVA
) = 0.556V). Tie the OVA input
to V
CC
= 3.3V to set the OV threshold to 115% above the
undervoltage threshold (V
OVA
= 1.072V). Select accurate
OV thresholds between 0.556V and 0.660V by connecting
and external resistor between OVA and ground (Figure 16).
Configure higher OV thresholds by connecting an external
resistor between OVA and V
CC
(Figure 17). These higher
thresholds are potentially less accurate due to variations
in V
CC
.
APPLICATIO S I FOR ATIO
WUU
U
Figure 16. External Resistor from OVA to Ground
Figure 17. External Resistor from OVA to V
CC
R
OVA
( )
100
0.66
V
OVA
(V)
V
OVA
(% ABOVE UNDERVOLTAGE THRESHOLD)
1.02
1.56
100k 1M1k 10k 10M
2928 G04
0.84
1.20
1.38
32
104
212
68
140
176
V
CC
= 6V
V
CC
= 5.5V
V
CC
= 5V
V
CC
= 4.5V
V
CC
= 4V
V
CC
= 3.5V
V
CC
= 3V
R
OVA
( )
100
0.56
V
OVA
(V)
V
OVA
(% ABOVE UNDERVOLTAGE THRESHOLD)
0.60
0.66
100k 1M1k 10k 10M
2928 G03
0.58
0.62
0.64
12
20
32
16
24
28