Datasheet

LTC2928
25
2928f
g. Undervoltage thresholds
The positive supply monitor undervoltage threshold at all
of the monitor inputs is 0.5V. Connect a resistive divider
from the sensed voltage to ground. Connect the tap point
to the respective high impedance monitor input. Specify
the required undervoltage threshold (UV
TH
) and calculate
the divider ratio using
RnB
RnA
UV V
V
TH
=
()
.
–
05
1
This application requires –6.5% undervoltage thresholds
for all supplies. For the 1.8V supply monitored on V3,
the undervoltage threshold is 1.683V (1.8V x 0.935). The
necessary divider ratio is
RB
RA V
3
3
1 683
05
1237
=≈
.
.
–.
A good choice for R3B is 23.7k and R3A is 10k. All sequence
thresholds are a percentage of the configured undervoltage
threshold. The remaining ratios are:
RB
RA V
RB
RA V
1
1
2 338
05
1368
2
2
1 403
05
11
=≈
=≈
.
.
–.
.
.
–
..
.
.
–.
81
4
4
3 086
05
1517
RB
RA V
=≈
h. Power-good timing
The “power-good” time defines the maximum time allowed
for all monitored voltages to reach their undervoltage
threshold when sequencing-up, or the sequence-down
threshold (when sequencing-down) with respect to the time
of the first enabled (disabled) supply. If the “power-good”
timer expires, a sequence fault occurs. The “power-good”
time (t
PTMR
) is set with a capacitor from the PTMR pin to
ground. Calculate the “power-good” capacitance from
CF
ts
M
PTMR
PTMR
()
()
.
=
40 Ω
For this application, the “power-good” time is 400ms,
yielding
C
ms
M
F
PTMR
==
400
40
01
.
.
Ω
µ
i. Reset delay time
The reset delay time is the additional time that RST is held
low after all monitor inputs are above their undervoltage
threshold. It is also the additional time that OV is held low
(after an overvoltage event) after all monitor inputs are
below their overvoltage threshold. When the reset timer
expires, RST and/or OV is allowed to pull high. The reset
delay time (t
RTMR
) is set with a capacitor from the RTMR
pin to ground. Calculate the reset capacitance from
CF
ts
M
RTMR
RTMR
()
()
.
=
40 Ω
For this application, the reset delay time is 190ms,
yielding
CF
ms
M
F
RTMR
()
.
.==
190
40
0 047
Ω
µ
j. Overvoltage thresholds
Configure the OVA pin to set the global overvoltage
thresholds. The application requires overvoltage thresholds
at approximately 25% above the nominal supply voltage.
For the 1.8V supply, the overvoltage threshold (OV
TH
)
equals 2.25V (1.8V x 1.25). Compute the required value
for V
OVA
from:
VV
RnA
RnARnB
OV V
OV
AT
H
()
•(
)=
+
For this application,
VV
k
kk
V
OVA
()
.
•. .=
+
=
10
10 23 7
2250667
From the curves in Figures 16 and 17, the approximate
value for V
OVA
is achieved by leaving the OVA pin open.
Since the other monitor inputs were configured for the
same relative undervoltage level, the relative overvoltage
levels for the other supplies are the same (+ 25%).
The application requires a fast shutdown upon overvoltage.
To generate a fault upon an overvoltage condition, tie OV to
F LT . The fault condition shuts down all controlled supplies.
APPLICATIO S I FOR ATIO
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