Datasheet

LTC2928
18
2928f
Using an Enable Line to Generate a Sequencing-Up Delay
APPLICATIO S I FOR ATIO
WUU
U
Another interesting application combines the usage of both
the CAS pin connection and the DONE—ON communica-
tions link. Figure 4 shows a two dimensional configura-
tion of four LTC2928s that allows for 16 supplies to be
sequenced in up to 16 time positions.
CAS
DONE
STMR
LTC2928
(MASTER/FIRST)
16 SUPPLIES, 16 TIME POSITIONS
ON
V
CC
DONE
STMR
LTC2928
(MASTER/NOT FIRST)
(SLAVE/FIRST) (SLAVE/FIRST)
ON
CAS
V
CC
DONE
LTC2928
ON
V
CC
DONE
LTC2928
ON
2928 F04
CAS CAS
Figure 4. Two-dimensional application.
In this application, both slave devices are clocked by the
masters through their CAS pins. Again, sequencing-up
begins with ON pulling high. Although the ON input is high
on the device in the lower right quadrant, sequencing-up
will not begin there until the first master (upper left), and
its slave are finished sequencing-up. At that time the
DONE pin will pull up the ON pin of the second master.
The second master and slave will then start sequencing
up their supplies.
V
CC
RT2
I
EN
(10uA)
C
DEL
EN2
V
2
LTC2928
2928 F05
Figure 5. Adjustable Sequencing Delay
An arbitrary delay between enables may be added by
using an enable pull-up current (10µA) to charge a delay
capacitor (Figure 5). Position the delay using an RT
resis-
tor. Assuming 100% sequencing thresholds (0.5V) and
a fully discharged delay capacitor (C
DEL
), the added time
delay (T
DEL
) is:
TmsCF
DELDEL
()
()
=•50 µ
Be sure to account for the extra delay when using the
power-good timer (PTMR).
Extending Sequencing Delay to Subsequent Supplies
Sequencing delays can be extended after certain events by
paralleling capacitance to the STMR pin. Figure 6 shows
one way to add capacitance after a particular enable output
pulls high.
RESISTOR LIMITS
GATE VOLTAGE
C
STMR
EN2
STMR
V
CC
LTC2928
C
ADD
2928 F06
Figure 6. Adding STMR capacitance