Datasheet

LTC2928
14
2928f
Table 3. Sequence Time Position Resistors (1%)
Position Number RT (kΩ)
1 95.3
2 42.2
3 24.3
4 15.0
5 9.53
6 6.04
7 3.40
8 1.50
Table 4. Sequencing Threshold Selection
(% of 0.5V for ADJ, % of REF for –ADJ)
Sequence-Up (%) Sequence-Down (%) SQT1 SQT2
100 100 V
CC
V
CC
100 67 Open V
CC
100 33 Open Open
100 10 Open GND
67 100 V
CC
Open
67 67 GND V
CC
67 33 GND Open
67 10 GND GND
33 100 V
CC
GND
* No shutdown debug mode. In this mode, any internal or external fault will halt the system with full fault reporting but all enabled supplies remain enabled.
Table 2. Master/Slave Configuration Pins
Master Slave First
Cascade Position
Not First
Cascade Position
RST Pulls F LT RST Does not
Pull F LT
No Shutdown
Debug Mode*
MS1 MS2
● ● ●
GND GND
● ● ●
GND Open
● ● ●
GND V
CC
● ● ●
Open GND
● ● ●
Open Open
● ● ●
Open V
CC
● ● ● ●
V
CC
GND
● ● ● ●
V
CC
Open
● ● ● ●
V
CC
V
CC
Table 1. Input Polarity Selection
V1 V2 V3 V4 VSEL
+ ADJ (0.5V) + ADJ (0.5V) + ADJ (0.5V) + ADJ (0.5V) GND
– ADJ (0V) + ADJ (0.5V) + ADJ (0.5V) + ADJ (0.5V) V
CC
good timer starts with the first enable output pulling low
and is cleared when the last supply monitor input crosses
its sequence-down threshold. A sequence-down fault pulls
F LT and all enable outputs low. Use a single capacitor from
PTMR to ground to select the power good time. To disable
the power good timer, tie PTMR to ground.
All comparator outputs pull low at the start of the
sequence-down phase (ON low). If a sequence-down fault
occurs, use the fault report capability to determine which
supply failed to meet threshold (or other source of fault).
Force all supplies down in an un-sequenced manner by
pulling F LT low (external fault). For more details refer to
the Applications Information and discussion on system
faults later in this document.
After the system has clocked through “time position 1”,
the last LTC2928 (defined by a 2.4k to 5.1k pull-up resis-
tor on DONE) releases the pull down on DONE and DONE
pulls high.
OPERATIO
U