Datasheet

LTC2923
17
2923fa
Layout Considerations
Be sure to place a 0.1µF bypass capacitor as near as
possible to the supply pin of the LTC2923. A 10Ω resistor
located near the FET and connected between the FET’s
gate and the external C
GATE
capacitor is recommended.
This will almost assuredly eliminate the troublesome high
frequency oscillations that can occur due to the FET
interacting with PCB parasitics.
To minimize the noise on the slave supplies’ outputs, keep
the traces connecting the FBx pins of the LTC2923 and the
feedback nodes of the slave supplies as short as possible.
In addition, do not route those traces next to signals with
fast transition times. In some circumstances it might be
advantageous to add a resistor near the feedback node of
the slave supply in series with the FBx pin of the LTC2923.
This resistor must not exceed:
R
VV
I
V
V
RR
SERIES
FB
MAX FB
FA FB
==
⎛
⎝
⎜
⎞
⎠
⎟
()
15 15
1
.– .
–||
This resistor is most effective if there is already a capacitor
at the feedback node of the slave supply (often a compen-
sation component). Increasing the capacitance on a slave
supply’s feedback node will further improve the noise
immunity, but could affect the stability and transient
response of the supply.
APPLICATIO S I FOR ATIO
WUUU
V
CC
OUT
FET
R
FA
R
FB
R
SERIES
C
GATE
10Ω
MINIMIZE
TRACE
LENGTH
V
CC
LTC2923
2923 F21
RAMP
FB1
GATE
GND
0.1µF
DC/DC
FB OUT
Figure 21. Layout Considerations
MASTER
1ms/DIV
2923 F18
Figure 18. Weak Resistive Load
1V/DIV
SLAVE2
SLAVE1
1V/DIV
1ms/DIV
2923 F20
ON
SLAVE2
SLAVE1
MASTER
Figure 20. ON Pin Delayed
Figure 19. Power Supply Start-Ups Delayed
1V/DIV
1ms/DIV 2923 F19
ON
SLAVE2
SLAVE1
MASTER