Datasheet

LTC2923
15
2923fa
Supply Sequencing Example
APPLICATIO S I FOR ATIO
WUUU
Figure 17. Supply Sequencing Example
In Figure 16, the slave 1 supply and the slave 2 supply are
sequenced instead of tracking. The 3.3V supply ramps up
at 100V/s with an external FET and serves as the master
signal. The 1.8V slave 1 supply ramps up at 1000V/s
beginning 10ms after the master signal starts to ramp up.
The 2.5V slave 2 supply ramps up at 1000V/s beginning
25ms after the master signal begins to ramp up. Note that
not every combination of ramp rates and delays is pos-
sible. Small delays and large ratios of slave ramp rate to
master ramp rate may result in solutions that require
negative resistors. In such cases, either the delay must be
increased or the ratio of slave ramp rate to master ramp
rate must be reduced. In this example, solving for the
slave 1 supply yields:
1. Set the ramp rate of the master signal.
From Equation 1:
C
A
Vs
nF
GATE
=
µ
=
10
100
100
/
2. Solve for the pair of resistors that provide the desired
slave supply behavior, assuming no delay.
From Equation 2:
Rk
Vs
Vs
k
TB
= Ω = Ω16 5
100
1000
165.•
/
/
.
10ms/DIV 2923 F16b
1V/DIV
10ms/DIV
2923 F16a
1V/DIV
Figure 16. Supply Sequencing (from Figure 17)
SLAVE2
SLAVE1
MASTER
From Equation 3:
R
V
V
k
V
k
V
k
k
TA
′
=
Ω
+
ΩΩ
= Ω
08
1 235
16 5
1 235
35 7
08
165
213
.
.
.
.
.
–
.
.
–.
3. Choose R
TA
to obtain the desired delay.
From Equation 4:
R
Vk
ms V s
k
TA
′′
=
Ω
= Ω
08 165
10 100
132
.•.
•/
.
From Equation 5:
R
TA
= – 2.13kΩ||1.32kΩ = 3.48kΩ
Q1
C
GATE
100nF
V
CC
R
ONB
138k
3.3V
R
TB1
1.65k
R
TB2
88.7k
R
FA1
35.7k
1.8V
SLAVE1
3.3V
MASTER
R
FB1
16.5k
R
TA2
36.5k
R
TA1
3.48k
R
ONA
100k
ON
RAMPBUF
TRACK1
TRACK2
FB1
GATE
LTC2923
GND
2923 F17
RAMP
DC/DC
IN
3.3V
3.3V
FB = 1.235V OUT
R
FA2
412k
2.5V
SLAVE2
R
FB2
887k
DC/DC
IN
FB = 0.8V OUT
FB2
0.1µF
10Ω