Datasheet
LTC2923
11
2923fa
APPLICATIO S I FOR ATIO
WUUU
3-Step Design Procedure
The following 3-step procedure allows one to complete a
design for any of the tracking or sequencing profiles
shown in Figures 1 to 4. A basic three supply application
circuit is shown in Figure 9.
1.
Set the ramp rate of the master signal
.
Solve for the value of C
GATE
, the capacitor on the GATE
pin, based on the desired ramp rate (V/s) of the master
supply, S
M
.
C
I
S
A
GATE
GATE
M
= ≈ µ where I
GATE
10
(1)
If the external FET has a gate capacitance comparable to
C
GATE
, then the external capacitor’s value should be
reduced to compensate for the FET’s gate capacitance.
If no external FET is used, tie the GATE and RAMP pins
together.
2.
Solve for the pair of resistors that provide the desired
ramp rate of the slave supply, assuming no delay
.
Choose a ramp rate for the slave supply, S
S
. If the slave
supply ramps up coincident with the master supply or
with a fixed voltage offset, then the ramp rate equals the
master supply’s ramp rate. Be sure to use a fast enough
ramp rate for the slave supply so that it will finish
ramping before the master supply has reached its final
supply value. If not, the slave supply will be held below
the intended regulation value by the master supply. Use
the following formulas to determine the resistor values
for the desired ramp rate, where R
FB
and R
FA
are the
feedback resistors in the slave supply and V
FB
is the
feedback reference voltage of the slave supply:
RR
S
S
TB FB
M
S
= •
(2)
R
V
V
R
V
R
V
R
TA
TRACK
FB
FB
FB
FA
TRACK
TB
′
=
+ –
(3)
where V
TRACK
≈ 0.8V.
Note that large ratios of slave ramp rate to master ramp
rate, S
S
/S
M
, may result in negative values for R
TA
′. If
sufficiently large delay is used in step 3, R
TA
will be
positive, otherwise S
S
/S
M
must be reduced.
3.
Choose R
TA
to obtain the desired delay
.
If no delay is required, such as in coincident and
ratiometric tracking, then simply set R
TA
= R
TA
′. If a
delay is desired, as in offset tracking and supply se-
quencing, calculate R
TA
′′ to determine the value of R
TA
where t
D
is the desired delay in seconds.
R
VR
tS
TA
TRACK TB
DM
′′
=
•
•
(4)
R
TA
= R
TA
′||R
TA
′′ (5)
the parallel combination of R
TA
′ and R
TA
′′
As noted in step 2, small delays and large ratios of slave
ramp rate to master ramp rate (usually only seen in
sequencing) may result in solutions with negative values
for R
TA
. In such cases, either the delay must be increased
or the ratio of slave ramp rate to master ramp rate must be
reduced.
Figure 9. Three Supply Application
Q1
C
GATE
V
CC
R
ONB
V
IN
R
TB1
R
TB2
R
FA1
SLAVE1
MASTER
R
FB1
R
TA2
R
TA1
R
ONA
ON FB1
GATE
LTC2923
GND
2923 F09
RAMP
R
FA2
SLAVE2
R
FB2
RAMPBUF
TRACK1
TRACK2
FB2
DC/DC
IN
V
IN
V
IN
FB OUT
DC/DC
IN
FB OUT
0.1µF
10Ω