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LTC2923

2923fa

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Flexible Power Supply Tracking

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Tracks Both Up and Down

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Power Supply Sequencing

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Supply Stability is Not Affected

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Controls Two Supplies Without Series FETs

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Controls a Third Supply With a Series FET

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Adjustable Ramp Rates

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Electronic Circuit Breaker

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Available in 10-Lead MS and 12-Lead

(4mm × 3mm) DFN Packages

Power Supply

Tracking Controller

■

CORE

and V

I/O

Supply Tracking

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Microprocessor, DSP and FPGA Supplies

■

Servers

■

Communication Systems

The LTC

2923 provides a simple solution to power supply

tracking and sequencing requirements. By selecting a few

resistors, the supplies can be configured to ramp-up and

ramp-down together or with voltage offsets, time delays

or different ramp rates.

By introducing currents into the feedback nodes of two

independent switching regulators, the LTC2923 causes

their outputs to track without inserting any pass element

losses. Because the currents are controlled in an open-

loop manner, the LTC2923 does not affect the transient

response or stability of the supplies. Furthermore, it

presents a high impedance when power-up is complete,

effectively removing it from the DC/DC circuit.

For systems that require a third supply, one supply can be

controlled with a series FET. This optional series FET can

also control a supply that does not allow direct access to

its feedback resistors (e.g., a power module) or a supply

whose output cannot be forced to ground (e.g., a 3-termi-

nal linear regulator). When the FET is used, an electronic

circuit breaker provides protection from short-circuit

conditions.

10nF

138k

3.3V

16.5k

887k

35.7k

1.8V

3.3V

16.5k

412k

13k

100k

RAMPBUF

TRACK1

TRACK2

FB1

GATE

LTC2923

GND

2923 TA01

RAMP

412k

2.5V

887k

DC/DC

FB = 1.235V OUT

DC/DC

FB = 0.8V OUT

FB2

SDO

STATUS

1V/DIV

1ms/DIV

2923 TA02

3.3V

2.5V

1.8V

1V/DIV

3.3V

2.5V

1.8V

1ms/DIV

2923 F08b

FEATURES

DESCRIPTIO

TYPICAL APPLICATIO

APPLICATIO S

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Patents Pending.

Summary of content (20 pages)

PAGE 1
LTC2923 Power Supply Tracking Controller U FEATURES DESCRIPTIO ■ The LTC®2923 provides a simple solution to power supply tracking and sequencing requirements. By selecting a few resistors, the supplies can be configured to ramp-up and ramp-down together or with voltage offsets, time delays or different ramp rates.
PAGE 2
LTC2923 W W W AXI U U ABSOLUTE RATI GS (Note 1) Supply Voltage (VCC) ................................ – 0.3V to 10V Input Voltages ON ........................................................ – 0.3V to 10V TRACK1, TRACK2 ...................... – 0.3V to VCC + 0.3V RAMP ........................................... – 0.3V to VCC + 1V Output Voltages FB1, FB2, SDO, STATUS ........................– 0.3V to 10V RAMPBUF ................................. – 0.3V to VCC + 0.3V GATE (Note 2) ....................
PAGE 3
LTC2923 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. 2.9V < VCC < 5.5V unless otherwise noted (Note 3). SYMBOL PARAMETER CONDITIONS VON(FC) ON Pin Fault Clear Threshold Voltage ION ON Pin Input Current ∆VDS(TH) FET Drain-Source Overcurrent Voltage Threshold (VCC – VRAMP) IRAMP RAMP Pin Input Current 0V < RAMP < VCC, VCC = 5.
PAGE 4
LTC2923 U W TYPICAL PERFOR A CE CHARACTERISTICS Specifications are at TA = 25°C unless otherwise noted. IGATE Fast Pull-Down vs Temperature ICC vs VCC ITRACKx = IFBx = –1mA IRAMPBUF = –2mA ITRACKx = IFBx = 0mA IRAMPBUF = 0mA 35 VCC = 5.5V ICC vs VCC 8.0 1.5 40 1.4 7.9 1.3 7.8 ICC (mA) IGATE (mA) 25 20 VCC = 2.9V 15 10 ICC (mA) 30 1.2 7.7 7.6 1.1 5 –25 0 50 25 TEMPERATURE (°C) 75 1.0 2.5 100 3 3.5 4.5 4 5 VTRACKx vs Temperature VTRACKx (V) VRAMPBUF(OL) (mV) VCC = 5.
PAGE 5
LTC2923 U U U PI FU CTIO S MS/DE Packages VCC (Pin 1): Positive Supply Input Pin. The operating supply input range is 2.9V to 5.5V. An undervoltage lockout circuit resets the part when the supply is below 2.5V. VCC should be bypassed to GND with a 0.1µF capacitor. ON (Pin 2): On Control Input. The ON pin has a threshold of 1.23V with 75mV of hysteresis. An active high will cause 10µA to flow from the GATE pin, ramping up the supplies.
PAGE 6
LTC2923 W FU CTIO AL BLOCK DIAGRA U U 1 VCC CHARGE PUMP 10µA 2 ON 1.2V 0.4V 10 + – – + GATE 11 (9) SHORT-CIRCUIT FAULT LATCH R Q S Q ONSIG 10µA STATUS GATE > RAMP + 4.9V 4.9V GATE RAMP > VCC VCC RAMP 12 (10) + – VCC – RAMP > 200mV 0.2V VCC RAMP < 100mV + – 9 SDO ONSIG VCC < 2.6V – + 5 RAMPBUF 0.1V VCC 2.6V 1× VCC 3 TRACK1 + – 0.8V FB1 8 VCC 4 TRACK2 + – 6 0.
PAGE 7
LTC2923 U W U U APPLICATIO S I FOR ATIO Power Supply Tracking and Sequencing The LTC2923 handles a variety of power-up profiles to satisfy the requirements of digital logic circuits including FPGAs, PLDs, DSPs and microprocessors. These requirements fall into one of the four general categories illustrated in Figures 1 to 4. Some applications require that the potential difference between two power supplies must never exceed a specified voltage.
PAGE 8
LTC2923 U W U U APPLICATIO S I FOR ATIO Tracking Cell In a properly designed system, when the master signal has reached its maximum voltage the current from the TRACKx pin is zero. In this case, there is no current from the FBx pin and the LTC2923 has no effect on the output voltage accuracy, transient response or stability of the slave supply. The LTC2923’s operation is based on the tracking cell shown in Figure 5, which uses a proprietary wide-range current mirror.
PAGE 9
LTC2923 U W U U APPLICATIO S I FOR ATIO VCC RONB ON 10µA + GATE RONA 1.2V – CGATE 10µA VCC +– Q1 + 200mV – RAMPBUF RAMP 1× MASTER VCC + 0.8V – RTB1 FB1 TRACK1 VCC RTA1 DC/DC RFA1 + SLAVE1 RFB1 0.8V – RTB2 FB2 TRACK2 DC/DC SLAVE2 RTA2 RFA2 RFB2 2923 F06 Figure 6. Simplified Functional Diagram The LTC2923 features an electronic circuit breaker function that protects the optional series FET against short circuits. When the FET is fully enhanced (GATE > RAMP + 4.
PAGE 10
LTC2923 U W U U APPLICATIO S I FOR ATIO Shutdown Output In some applications it might be necessary to control the shutdown or RUN/SS pins of the slave supplies using the 12-lead LTC2923CDE or LTC2923IDE. The LTC2923 may not be able to supply the rated 1mA of current from the FB1 and FB2 pins when VCC is below 2.9V. If the slave power supplies are capable of operating at low input voltages, use the open-drain SDO output to drive the SHDN or RUN/SS pins of the slave supplies (see Figure 7).
PAGE 11
LTC2923 U W U U APPLICATIO S I FOR ATIO 3-Step Design Procedure The following 3-step procedure allows one to complete a design for any of the tracking or sequencing profiles shown in Figures 1 to 4. A basic three supply application circuit is shown in Figure 9. Note that large ratios of slave ramp rate to master ramp rate, SS/SM, may result in negative values for RTA′. If sufficiently large delay is used in step 3, RTA will be positive, otherwise SS/SM must be reduced. 3.
PAGE 12
LTC2923 U W U U APPLICATIO S I FOR ATIO Coincident Tracking Example MASTER SLAVE2 SLAVE1 1V/DIV 1ms/DIV 1V/DIV 1ms/DIV 2923 F10a 2923 F10b Figure 10. Coincident Tracking (from Figure 11) A typical three supply application is shown in Figure 11. The master signal is a 3.3V module. The slave 1 supply is a 1.8V switching power supply and the slave 2 supply is a 2.5V switching power supply. Both slave supplies track coincidently with the 3.3V supply that is controlled with an external FET.
PAGE 13
LTC2923 U W U U APPLICATIO S I FOR ATIO Ratiometric Tracking Example SLAVE2 SLAVE1 1V/DIV 1ms/DIV 1V/DIV 1ms/DIV 2923 F12a 2923 F12b Figure 12. Ratiometric Tracking (from Figure 13) This example converts the coincident tracking example to the ratiometric tracking profile shown in Figure 12, using two supplies without an external FET.
PAGE 14
LTC2923 U W U U APPLICATIO S I FOR ATIO Offset Tracking Example MASTER SLAVE2 SLAVE1 1V/DIV 1ms/DIV 1V/DIV 1ms/DIV 2923 F14a 2923 F14b Figure 14. Offset Tracking (from Figure 15) Converting the circuit in the coincident tracking example to the offset tracking shown in Figure 14 is relatively simple. Here the 1.8V slave 1 supply ramps up 1V below the master. The ramp rate remains the same (1000V/s), so there are no changes necessary to steps 1 and 2 of the 3-step design procedure.
PAGE 15
LTC2923 U W U U APPLICATIO S I FOR ATIO Supply Sequencing Example MASTER SLAVE2 SLAVE1 1V/DIV 10ms/DIV 1V/DIV 10ms/DIV 2923 F16a 2923 F16b Figure 16. Supply Sequencing (from Figure 17) In Figure 16, the slave 1 supply and the slave 2 supply are sequenced instead of tracking. The 3.3V supply ramps up at 100V/s with an external FET and serves as the master signal. The 1.8V slave 1 supply ramps up at 1000V/s beginning 10ms after the master signal starts to ramp up. The 2.
PAGE 16
LTC2923 U W U U APPLICATIO S I FOR ATIO Final Sanity Checks The collection of equations below is useful for identifying unrealizable solutions. As stated in step 2, the slave supply must finish ramping before the master signal has reached its final voltage. This can be verified by the following equation: ⎛ R ⎞ VTRACK ⎜ 1 + TB ⎟ < VCC, where VTRACK = 0.
PAGE 17
LTC2923 U W U U APPLICATIO S I FOR ATIO Layout Considerations MASTER SLAVE2 1V/DIV SLAVE1 1ms/DIV 2923 F18 Figure 18. Weak Resistive Load MASTER SLAVE1 1V/DIV SLAVE2 Be sure to place a 0.1µF bypass capacitor as near as possible to the supply pin of the LTC2923. A 10Ω resistor located near the FET and connected between the FET’s gate and the external CGATE capacitor is recommended.
PAGE 18
LTC2923 U PACKAGE DESCRIPTIO MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 10 9 8 7 6 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) DETAIL “A” 0.497 ± 0.076 (.0196 ± .003) REF 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 1.10 (.
PAGE 19
LTC2923 U PACKAGE DESCRIPTIO DE Package 12-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1695) 0.65 ±0.05 3.50 ±0.05 1.70 ±0.05 2.20 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 3.30 ±0.05 (2 SIDES) 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 ±0.10 (2 SIDES) 7 R = 0.115 TYP 0.38 ± 0.10 12 R = 0.20 TYP PIN 1 TOP MARK (NOTE 6) 3.00 ±0.10 (2 SIDES) 1.70 ± 0.10 (2 SIDES) PIN 1 NOTCH (UE12/DE12) DFN 0603 0.200 REF 0.75 ±0.05 0.00 – 0.05 6 0.25 ± 0.05 3.30 ±0.
PAGE 20
LTC2923 U TYPICAL APPLICATIO S Daisy-Chained Application High Voltage Supply Application 3.3V 3.3V 0.1µF 0.1µF GATE VCC ON FB1 IN DC/DC FB = 1.235V OUT CGATE 10nF 3.3V SLAVE1 RONB 138k LTC2923 RFB1 RFA1 RAMPBUF RONA 100k VCC GATE ON RAMP FB1 TRACK1 RTB2 FB2 TRACK2 GND RTA2 IN DC/DC FB = 0.8V OUT RFA1 RAMPBUF RAMP TRACK1 RTA1 RTB2 FB2 TRACK2 RTA2 RFA2 IN DC/DC FB = 0.8V OUT RFA2 0.1µF RAMP ON RFB2 2923 TA04 CGATE 10nF RONA 100k 5V SLAVE2 GND 3.