Datasheet

LTC2919
12
2919f
To minimize errors arising from ADJ input bias and to
minimize loading on REF choose resistor R
P1
(for positive
supply monitoring) or R
N1
(for negative supply monitoring)
in the range of 5k to 100k.
For a positive-monitoring application, R
P2
is then chosen
by:
R
P2
= R
P1
(2V
TRIP
– 1)
For a negative-monitoring application:
R
N2
= R
N1
(1 – 2V
TRIP
)
Note that the value V
TRIP
should be negative for a negative
application.
The LTC2919 can also be used to monitor a single supply
for both UV and OV. This may be accomplished with three
resistors, instead of the four required for two independent
supplies. Confi gurations are shown in Figures 3 and 4. R
P4
or R
N4
may be chosen as is R
P1
or R
N1
above.
For a given R
P4
, monitoring a positive supply:
R
P5
= R
P4
V
OV
–V
UV
V
UV
R
P6
= R
P4
2V
UV
–1
()
V
OV
V
UV
For monitoring a negative supply with a given R
N4
:
R
N5
= R
N4
V
UV
–V
OV
1– V
UV
R
N6
= R
N4
1– 2V
UV
()
1– V
OV
1– V
UV
For example, consider monitoring a –5V supply at ±10%. For
this supply application: V
OV
= –5.575V and V
UV
= –4.425V.
Suppose we wish to consume about 5A in the
divider, so
R
N4
= 100k. We then fi nd R
N5
= 21.0k, R
N6
= 1.18M (nearest
1% standard values have been chosen).
V
CC
Monitoring/UVLO
The LTC2919 contains an accurate third -10% undervoltage
monitor on the V
CC
pin. This monitor is fi xed at a nominal
11.5% below the V
CC
specifi ed in the part number. The
standard part (LTC2919-2.5) is confi gured to monitor a
2.5V supply (UVLO threshold of 2.213V), but versions
to monitor 3.3V and 5.0V (UVLO of 2.921V and 4.425V,
respectively) are available.
For applications that do not need V
CC
monitoring, the
2.5V version should be used, and the UVLO will simply
guarantee that the V
CC
is above the minimum required for
proper threshold and timer accuracy before the timeout
begins.
Setting the Reset Timeout
RST goes high after a reset timeout period set by the TMR
pin when the V
CC
and ADJ inputs are valid. This reset
timeout may be confi gured in one of three ways: internal
200ms, programmed by external capacitor and no timeout
(comparator mode).
In externally-controlled mode, the TMR pin is connected
by a capacitor to ground. The value of that capacitor allows
for selection of a timeout ranging from about 400s to 9
seconds. See the following section for details.
APPLICATIO S I FOR ATIO
WUU
U
–
+
–
+
+
–
0.5V
2919 F03
ADJ1
OUT1
OUT2
UV
OV
ADJ2
V
MON
R
P5
R
P6
R
P4
LOGIC
&
OPEN
DRAIN
MOSFET
LOGIC
&
OPEN
DRAIN
MOSFET
Figure 3. Setting UV and OV Trip Point for a Positive Supply
–
+
–
+
+
–
0.5V
2919 F04
ADJ2
ADJ1
REF
–V
MON
R
N5
R
N4
R
N6
OUT1
OUT2
OV
UV
LOGIC
&
OPEN
DRAIN
MOSFET
LOGIC
&
OPEN
DRAIN
MOSFET
Figure 4. Setting UV and OV Trip Point for a Negative Supply