Datasheet

LTC2917/LTC2918
8
29178fb
BLOCK DIAGRAM
+
–
GND
RST
V
CC
V
CC
V
CC
29178 BD
VM
SEL1 MRSEL2 RT
3 STATE
DECODE
MONITOR
DIVIDER
MATRIX
REFERENCE
DIVIDER
MATRIX
INTERNAL
200ms TIMER
ADJUSTABLE
RESET TIMER
RESET
DRIVER LOGIC
V
CC
DETECT
TOL
6.2V
100k
0.5V
+
–
WT WDI
V
CC
DETECT
INTERNAL
1.6 SECOND
TIMER
ADJUSTABLE
WATCHDOG
TIMER
WATCHDOG
LOGIC
LTC2918LTC2917
TIMING DIAGRAMS
VM
RST
V
MTx
1V
t
UV
t
RST
29178 TD01
Monitor Input Timing
WDI
RST
t
WDU
t
RST
29178 TD01
Watchdog Timing (LTC2917-A, LTC2918-A)
WDI
RST
t
WDU
t > t
WDL
t
RST
29178 TD03
t
RST
t < t
WDL
Watchdog Timing (LTC2917-B, LTC2918-B)