Datasheet

LTC2914
9
2914fc
For more information www.linear.com/LTC2914
Voltage Monitoring
The LTC2914 is a low power quad voltage monitoring cir-
cuit with
four undervoltage and four overvoltage inputs. A
timeout period
that holds OV or UV asserted after all faults
have cleared is adjustable using an external capacitor and
is externally disabled.
Each voltage monitor has two inputs (VHn and VLn) for
detecting undervoltage and overvoltage conditions. When
configured to monitor a positive voltage V
n
using the
3-resistor circuit configuration shown in Figure 1, V Hn is
connected to the high-side tap of the resistive divider and
VLn is connected to the low-side tap of the resistive divider.
If an input is configured as a negative voltage monitor, the
outputs UV
n
and OV
n
in Figure 1 are swapped internally. V
n
is then connected as shown in Figure 2. Note, VHn is still
connected to the high-side tap and VLn is still connected
to the low-side tap.
Polarity Selection
The three-state polarity-select pin (SEL) selects one of three
possible polarity combinations for the input thresholds,
as described in Table 1. When an input is configured for
negative supply monitoring, VHn is configured to trigger an
overvoltage condition and VLn is configured to trigger an
undervoltage
condition. With this configuration,
an OV con-
dition occurs when the
supply voltage is more negative than
the configured threshold and a UV condition occurs when
the voltage is less negative than the configured threshold.
The three-state input pin SEL is connected to GND, V
CC
or
left unconnected during normal operation. When the pin
is left unconnected, the maximum leakage allowed from
the pin is ±10µA to ensure it remains in the open state.
Table 1 shows the three possible selections of polarity
based on the SEL pin connection.
Table 1. Voltage Polarity Programming (V
UOT
= 0.5V Typical)
SEL V3 INPUT V4 INPUT
V
CC
Positive
VH3 < V
UOT
→ UV
VL3 > V
UOT
→ OV
Positive
VH4 < V
UOT
→ UV
VL4 > V
UOT
→ OV
Open Positive
VH3 < V
UOT
→ UV
VL3 > V
UOT
→ OV
Negative
VH4 < V
UOT
→ OV
VL4 > V
UOT
→ UV
GND Negative
VH3 < V
UOT
→ OV
VL3 > V
UOT
→ UV
Negative
VH4 < V
UOT
→ OV
VL4 > V
UOT
→ UV
3-Step Design Procedure
The following 3-step design procedure allows selecting
appropriate resistances to obtain the desired UV and OV trip
points for the positive voltage monitor circuit in Figure 1
and the negative voltage monitor circuit in Figure 2. 1%
resistor tolerances are suggested to maintain the ±1.5%
threshold accuracy.
Figure 1. 3-Resistor Positive UV/OV Monitoring Configuration
Figure 2. 3-Resistor Negative UV/OV Monitoring Configuration
applicaTions inForMaTion
–
+
–
+
+
–
0.5V
LTC2914
UV
n
VHn
R
C
R
B
R
A
2914 F01
V
n
VLn
OV
n
–
+
–
+
+
–
+
–
0.5V
1V
LTC2914
UV
n
VHn
REF
R
A
R
B
R
C
2914 F02
VLn
V
n
OV
n
–
+