Datasheet
LTC2913
10
2913fb
APPLICATIONS INFORMATION
where R
PD
is the on-resistance of the internal pull-down
transistor, typically 50Ω at V
CC
> 1V and at room tem-
perature (25°C). C
LOAD
is the external load capacitance
on the pin. Assuming a 150pF load capacitance, the fall
time is 16.5ns.
The rise time on the UV and OV pins is limited by a 400k
pull-up resistance to V
CC
. A similar formula estimates the
output rise time (10% to 90%) at the UV and OV pins:
t
RISE
≈ 2.2 • R
PU
• C
LOAD
where R
PU
is the pull-up resistance.
OV Latch (LTC2913-1)
With the LATCH pin held low, the OV pin latches low when
an OV condition is detected. The latch is cleared by raising
the LATCH pin high. If an OV condition clears while LATCH
is held high, the latch is bypassed and the OV pin behaves
the same as the UV pin with a similar timeout period at the
output. If LATCH is pulled low while the timeout period is
active, the OV pin latches as before.
Disable (LTC2913-2)
The LTC2913-2 allows disabling the UV and OV outputs
via the DIS pin. Pulling DIS high will force both outputs
to remain weakly pulled high, regardless of any faults
that occur on the inputs. However, if a UVLO condition
occurs, UV asserts and pulls low, but the timeout function
is bypassed. UV pulls high as soon as the UVLO condition
is cleared.
DIS has a weak 2μA (typical) internal pull-down current
guaranteeing normal operation with the pin left open.
Dual UV/OV Supply Monitor, 10% Tolerance, 5V, 3.3V
Supply Monitor Powered from 12V, 10% Tolerance, 12V, 5V
R
C2
27.4k
R
B1
1k
R
C1
44.2k
10
6
7
8
95
4
3
2
1
VH1
VL1
VH2
GND TMR
SYSTEM
POWER
SUPPLIES
VL2
OV
UV
2913 TA02
LATCH
R
A2
4.53k
C
TMR
22nF
TIMEOUT = 200ms
R
B2
1k
R
A1
4.53k
V
CC
LTC2913-1
C
BYP
0.1μF
5V
3.3V
R
C2
44.2k
R
B1
1k
R
C1
115k
R
Z
10k
10
6
7
8
9
5
4
3
2
1
VH1
VL1
VH2
GND
TMR
SYSTEM
POWER
SUPPLIES
VL2
OV
UV
2913 TA03
DIS
R
A2
4.53k
R
B2
1k
R
A1
4.53k
V
CC
LTC2913-2
C
BYP
0.1μF
12V
5V
TYPICAL APPLICATIONS