Datasheet

LTC2911
8
2911f
TIMING DIAGRAMS
Input Valid to Latch Enable
Setup and Hold Timing
t
RST
V
TMR(LATCH)
V
TMR(LATCH)
+
∆V
TMR(LATCH)
2911 TD04
t > t
SU,MON
1V
RST
ADJ, V1, V2
TMR
V
RTX
t
SU,MON
t
HD,MON
LATCH IN
NOTE: FOR THE LTC2911-5, V1 LOW RESETS RST TO A LOW STATE
–3% OVERDRIVE
INPUT RETURNING TO ABOVE V
RTX
FOR t > t
SU,MON
, RST PIN STAYS HIGH
3% OVERDRIVE
MARGINING
POWER UP
Input Valid to Latch Release
Setup Timing
Input Invalid to Latch Enable
Setup and Hold Timing
Input Invalid to Latch
Release Setup Timing
TMR
RST
ADJ, V1, V2
t
SU,MON
t
UV
t
HD,MON
LATCH IN
NOTE: FOR THE LTC2911-5, V1 LOW RESETS RST TO A LOW STATE
V
TMR(LATCH)
V
RTX
1V
V
TMR(LATCH)
+
∆V
TMR(LATCH)
t > t
SU,MON
V
RTX
–3% OVERDRIVE
2911 TD05
–3% OVERDRIVE
3% OVERDRIVE
MARGINING
INPUT RETURNING TO BELOW V
RTX
FOR t > t
SU,MON
, RST PIN STAYS LOW
Undervoltage and Reset Timing
Latch Release to RST Low Timing
V
RTX
t
UV
t
RST
1.0V
2911 TD01
V
X
RST
RST
TMR 0.4V
1.0V
2911 TD02
NOTE: ADJ FORCED LOW BEFORE TMR RELEASE
t
P,LR
Power-Fail Timing
PFI
V
PFT
t
P,PF
t
P,PF
1.0V
2911 TD03
PFO
Latching RST High
Latching RST Low