Datasheet

LTC2911
4
2911f
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
ADJ
= 0.55V, V
PFI
= 0.55V, V1 = 3.3V unless otherwise noted. (Notes 2, 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
P,PF
PFI Comparator Propagation Delay to PFO V
PFI
Driven Beyond Threshold
V
PFT
by More Than 10%
l
8 30 80 µs
t
UV
V1, V2, ADJ Undervoltage Detect to RST Low V
X
Less Than Threshold V
RTX
by
More Than 10%
l
8 30 80 µs
V
OH
RST, PFO Output Voltage High (Note 5) I
RST
= –1µA
l
V1 – 1 V1 V
V
OL
RST, PFO Output Voltage Low (Note 6) V
CC
= 0.5V, I = 5µA
V
CC
= 1V, I = 100µA
V
CC
= 3V, I = 2.5mA
l
l
l
0.01
0.01
0.10
0.15
0.15
0.30
V
V
V
t
RST(EXT)
Reset Timeout Period, External C
TMR
= 2.2nF
l
15 20 27 ms
t
RST(INT)
Reset Timeout Period, Internal V
TMR
= V1
l
140 200 280 ms
V
TMR(INT)
Timer Internal Mode Threshold V
TMR
Rising
l
V1 – 0.40 V1 – 0.020 V1 – 0.10 V
∆V
TMR(INT)
Timer Internal Mode Hysteresis V
TMR
Falling
l
40 100 160 mV
V
TMR(LATCH)
Timer Latch Mode Threshold V
TMR
Falling
l
0.10 0.20 0.40 V
∆V
TMR(LATCH)
Timer Latch Mode Hysteresis V
TMR
Rising
l
40 75 160 mV
t
P, LR
Latch Release Propagation Delay to RST Low V
TMR
Rising, Step 0V to 0.6V
l
0.5 3 µs
t
SU,MON
Monitor Input Setup Time to Latch Enable (Note 7)
Monitor Input Setup Time to Latch Release
V
TMR
Falling, Step 0.6V to 0V
V
TMR
Rising, Step 0V to 0.6V
l
2 ms
t
HD, MON
Monitor Input Hold Time to Latch Enable
Monitor Input Hold Time to Latch Release
V
TMR
Falling, Step 0.6V to 0V
V
TMR
Rising, Step 0V to 0.6V
l
0 µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise noted.
Note 3: The internal supply voltage (V
CC
) is generated from the greater of
the voltages on the V1 and V2 inputs. V
CC
= V1 for the LTC2911-5.
Note 4: Under typical operating conditions, quiescent current is drawn
from the greater of the voltages on the V1 and V2 inputs. For the
LTC2911-5 only V1 supplies the quiescent current.
Note 5: The RST and PFO output pins on the LTC2911 have internal pull-
ups to V1. However, for faster rise times or for V
OH
voltages greater than
V1, use an external pull-up resistor.
Note 6: The RST and PFO pull-down currents are derived from V1 and V2
except for the LTC2911-5 where the pull-down strength is derived only
from V1.
Note 7: t
SU,MON
is required to latch a low RST state and t
SU,MON
+ t
RST
is
required to latch a high RST state.