Datasheet

LTC2911
13
2911f
Resistor Selection for Combined Reset
and Power-Fail Divider
When the power-fail and reset signals are based on the
same supply, the PFI and ADJ inputs may be connected
to a single resistive divider formed from three resistors.
The configuration is shown in Figure 4. For a given bias
current I, R
A
, R
B
and R
C
can be calculated from:
R
A
=
0.5V
I
R
B
= R
A
•
V
TRIP_ PFI_FALL
V
TRIP _ ADJ
– 1






R
C
= R
A
•
V
TRIP_ ADJ
0.5V
– 1






•
V
TRIP_ PFI_FALL
V
TRIP_ ADJ






For example, consider monitoring a 5V, ±5% supply with
V
TRIP_PFI_FALL
= 4.5V and V
TRIP_ADJ
= 4V. The resulting
V
TRIP_PFI_RISE
is equal to 4.63V or 3% above V
TRIP_PFI_FALL
.
The maximum V
TRIP_PFI_RISE
should not overlap the mini-
mum power supply voltage level for PFO to deassert when
the supply recovers. Mathematically, after factoring in the
sum of the power supply tolerance and the LTC2911 toler-
ance, the V
TRIP_PFI_RISE
should be lower than 5V – 6.5%.
APPLICATIONS INFORMATION
See Threshold Accuracy section for more details. In the
design, if we wish to consume about 5µA in the divider,
R
A
= 100k. We then find R
B
= 12.4k and R
C
= 787k (nearest
1% standard values).
Setting the Reset Timeout
RST goes high after the V1, V2 and ADJ inputs are above
their thresholds for a reset timeout period. Connecting
the TMR pin to V1 enables the internal 200ms timer.
To configure a different reset timeout period connect a
capacitor between the TMR pin and ground.
The following formula approximates the value of capacitor
needed for a particular timeout:
C
TMR
= t
RST
• 106.5 [pF/ms]
Leaving the TMR pin open with no external capacitor
generates a reset timeout of approximately 400µs. Larger
capacitors may be used to increase the timeout, but the
capacitor leakage current must not exceed 500nA. Other-
wise, the timer accuracy will be severely affected.
Suitable values of C
TMR
for a given t
RST
may be selected
from Figure 5.
–
+
–
+
+
–
0.5V
2911 F04
PFI
ADJ
LTC2911
R
B
R
C
R
A
V
TRIP
Figure 4. Combining PFI/ADJ Monitoring of One Supply
with Three Resistors
Figure 5. External Timeout vs C
TMR
C
TMR
(F)
10p
0.1
EXTERNAL TIMEOUT, t
RST
(ms)
10
10000
100p 1n 10n 100n 1µ
2911 F05
1
100
1000