Datasheet

LTC2875
14
Rev A
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APPLICATIONS INFORMATION
Common Mode Voltage vs Supply Voltage
When operating from a 5V supply the LTC2875 adheres to
the ISO 11898-2 CAN bus standard by maintaining drive
levels that are symmetric around V
CC
/2 = 2.5V. An internal
common mode reference of V
CC
/2 is buffered to supply
the termination of the receiver input resistors. A second
buffer with a high voltage tolerant output supplies V
CC
/2
to the SPLIT output.
When operating from a 3.3V supply the 2.5V nominal
common mode voltage specified in the ISO 11898-2 stan-
dard is too close to the 3.3V supply to provide symmetric
drive levels while maintaining the necessary differential
output voltage. To maintain driver symmetry the common
mode reference voltage is lowered during 3.3V operation.
The typical output common mode voltage is 1.95V in the
dominant state. The internal common mode reference is
set to V
CC
/2 + 0.3V = 1.95V to match the dominant state
output common mode voltage. This reference is indepen-
dently buffered to supply the termination of the receiver
input resistors and the SPLIT voltage output.
As the LTC2875 operates over a very wide common
mode range, this small shift of –0.55V in the common
mode when operating from 3.3V does not degrade data
transmission or reception. An LTC2875 operating at 3.3V
may share a bus with other CAN transceivers operating
at 5V. However, the electromagnetic emissions may be
larger if transceivers powered by different voltages share
a bus, due to the fluctuation in the common mode volt-
age from 1.95V (when an LTC2875 on a 3.3V supply is
dominant) to
2.5V (when a CAN transceiver on a 5V sup-
ply is dominant).
RS Pin and V
ariable Slew Rate Control
The driver features adjustable slew rate for improved EME
performance. The slew rate is set by the amount of cur-
rent that is sourced by the RS pin when it is pulled below
approximately 1.1V
. This allows the slew rate to be set
by a single slew control resistor RSL in series with the
RS pin (Figure1).
The relationship between the series slew control resistor
RSL and the transmitter slew rate can be observed in
Figure10. RSL ≤ 4kΩ is recommended for high data rate
communication. RSL should be less than 200k to ensure
that the RS pin can be reliably pulled below V
IL_RS
to
enable the chip.
Figure10. Slew Rate vs Slew Control Resistor RSL
Figure11. Equivalent Circuit of RS Pin
When a voltage between 1.1V and V
CC
is applied, the RS
pin acts as a high impedance receiver. A voltage above
V
IH_RS
puts the chip in shutdown, while a voltage below
V
IL_RS
but above 1.1V activates the chip and sets the
transmitter to the minimum slew rate.
RSL (kΩ)
SLEW RATE (V/µs)
2875 F10
60
50
40
30
20
10
0
1 10 100
V
CC
= 5V
V
CC
= 3.3V
The slew control circuit on the RS pin is activated at applied
voltages below 1.1V. The RS pin can be approximately
modeled as a 1.1V voltage source with a series resistance
of 2kΩ and a current compliance limit of –100µA, and
a 250kΩ pull-up resistor to V
CC
(Figure11). Lowering
2875 F11
I
SC
(–100µA LIMIT)
RS
I
PU
V
CC
IDEAL
DIODE
2k
1.1V
+
–
V
250k
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