Datasheet

LTC2870/LTC2871
23
28701fb
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applicaTions inForMaTion
This windowing around 0V preserves pulse width and
duty cycle for small input signals with heavily slewed
edges, typical of what might be seen at the end of a very
long cable. This performance is highlighted in Figure17,
where a signal is driven through 4000 feet of CAT5e cable
at 3Mbps
. Even though the differential signal peaks at just
over ±200mV and is heavily slewed, the output maintains a
nearly perfect signal with almost no duty cycle distortion.
An additional benefit of the window comparator architec-
ture is excellent noise immunity due to the wide effec-
tive differential hysteresis (or ‘AC’ hysteresis) of about
220mV for normal signals transitioning through the win-
dow region in less than approximately 0.7µs. Increasingly
slower signals will have increasingly less effective hys-
teresis, limited by the DC failsafe value of about 35mV.
The LTC2870 and LTC2871 provide full failsafe opera-
tion that guarantees the receiver output will be a logic
high state when the inputs are shorted, left open, or ter-
minated but not driven, for more than about 0.7µs. The
delay allows normal data signals to transition through the
threshold region without being interpreted as a failsafe
condition.
RS485 Biasing Resistors Not Required
RS485 networks are often biased with a resistive divider
to generate a differential voltage of ≥200mV on the data
lines, which establishes a logic high state when all the
transmitters on the network are disabled. The values of
the biasing resistors depend on the number and type of
transceivers on the line and the number and value of ter
-
minating resistors. Therefore the values of the biasing
resistors must be customized to each specific network
installation, and may change if nodes are added to or
removed from the network.
The internal failsafe feature of the LTC2870 and LTC2871
eliminates the need for external biasing resistors. The
LTC2870 and LTC2871 transceivers will operate correctly
on unbiased, biased or underbiased networks.
If a twisted pair has unbalanced capacitance from its two
conductors to AC ground, common mode transients can
translate into small differential voltages. If the common
mode event is large and fast enough, the resulting dif-
ferential voltage can cause a receiver, whose inputs are
undriven, to change state momentarily. In these extreme
conditions, high quality shielded cable is recommended.
If necessary, biasing resistors can be used on the bus to
pull the resting signal farther from the receivers failsafe
threshold.
Receiver Outputs
The RS232 and RS485 receiver outputs are internally
driven high (to V
L
) or low (to GND) with no external pull-
up needed. When the receivers are disabled the output pin
becomes Hi-Z with leakage of less than ±5μA for voltages
within the V
L
supply range.
Figure17. A 3Mbps Signal Driven Down 4000ft of CAT 5e
Cable. Top Traces: Received Signals After Transmission
Through Cable; Middle Trace: Math Showing Differences
of Top Two Signals; Bottom Trace: Receiver Output
(A-B)
200mV/DIV
B
100mV/DIV
A
RO
5V/DIV
28701 F16
200ns/DIV
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