Datasheet

LTC2756
5
2756f
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: Calculation from feedback resistance and I
OUT1
leakage current
specifications; not production tested. In most applications, unipolar zero-
scale error is dominated by contributions from the output amplifier.
Note 4: Input resistors measured from R
IN
to R
COM
; feedback resistors
measured from R
COM
to REF.
Note 5: DAC input resistance is independent of code.
Note 6: Parallel combination of the resistances from the specified pin to
I
OUT1
and from the specified pin to I
OUT2
.
Note 7: Using LT1468 with C
FEEDBACK
= 27pF. A ±0.0004% settling time
of 1.8µs can be achieved by optimizing the time constant on an individual
basis. See Application Note 120, 1ppm Settling Time Measurement for a
Monolithic 18-Bit DAC.
TiMing characTerisTics
The l denotes specifications that apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C.
Note 8: Measured at the major carry transition, 0V to 5V range. Output
amplifier: LT1468; C
FB
= 50pF.
Note 9: Full-scale transition; REF = 0V.
Note 10: REF = 6V
RMS
at 1kHz. 0V to 5V range. DAC code = FS. Output
amplifier = LT1468.
Note 11: Calculation from V
n
= √4kTRB, where k = 1.38E-23 J/°K
(Boltzmann constant), R = resistance (Ω), T = temperature (°K), and B =
bandwidth (Hz). 0V to 5V Range; zero-, mid-, or full-scale.
Note 12: Guaranteed by design; not production tested.
Note 13: When using SRO, maximum SCK frequency f
MAX
is limited by
SRO propagation delay t
9
as follows:
f
MAX
=
1
2 t
9
+ t
S
( )








, where t
S
is the setup time of the receiving device.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
7
CS/LD Low to SCK Positive Edge
l
5 ns
t
8
CS/LD High to SCK Positive Edge
l
5 ns
t
9
SRO Propagation Delay C
LOAD
= 10pF
l
26 ns
t
10
CLR Pulse Width Low
l
60 ns
t
11
LDAC Pulse Width Low
l
20 ns
t
12
CLR Low to RFLAG Low C
LOAD
= 10pF (Note 12)
l
70 ns
t
13
CS/LD High to RFLAG high C
LOAD
= 10pF (Note 12)
l
60 ns
SCK Frequency 50% Duty Cycle (Note 13)
l
25 MHz