Datasheet

LTC2633
15
2633fb
Block Diagram
test circuit
Test circuits for I
2
C digital I/O (see Electrical Characteristics)
Test Circuit 1 Test Circuit 2
timing Diagram
Figure 1. I
2
C Timing
Figure 2. Typical LTC2633 Write Transaction
2633 BD
I
2
C INTERFACE
I
2
C
ADDRESS
DECODE
POWER-ON
RESET
CONTROL
DECODE LOGIC
REGISTER REGISTER REGISTER REGISTER
DAC B
DAC A
V
OUTB
REF
SCL
SDACA0
V
OUTA
V
CC
GND
INTERNAL
REFERENCE
SWITCH
V
REF
2633 TC01
CA0
V
IH(CA0)
/V
IL(CA0)
100Ω
2633 TC02
CA0
GND
R
INH
/R
INL/
R
INF
V
DD
SCL
SDA
2633 F01
t
LOW
t
f
t
f
t
r
t
HD(STA)
t
HD(DAT)
S S P S
t
SU(STA)
t
SU(STO)
t
BUF
t
r
t
SU(DAT)
t
HD(STA)
t
SP
t
HIGH
ALL VOLTAGE LEVELS REFER TO V
IH(MIN)
AND V
IL(MAX)
LEVELS
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SDA A6 A5 A4 A3 A2 A1 A0 C3 C2 C1 C0 A3 A2 A1 A0W ACK ACK ACK ACKXXXX
START
SLAVE ADDRESS 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE
2633 F02
SCL