Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - DA converter (DAC) DFN 10

LTC2601/LTC2611/LTC2621

2601fa

16-/14-/12-Bit Rail-to-Rail

DACs in 10-Lead DFN

The LTC

2601/LTC2611/LTC2621 are single 16-, 14-

and 12-bit,

2.5V-to-5.5V rail-to-rail voltage output DACs

in a 10-lead DFN package. They have built-in high perfor-

mance output buffers and are guaranteed monotonic.

These parts establish new board-density benchmarks for

16- and 14-bit DACs and advance performance standards

for output drive and load regulation in single-supply,

voltage-output DACs.

The parts use a simple SPI/MICROWIRE compatible 3-wire

serial interface which can be operated at clock rates up to

50MHz. Daisy-chain capability, hardware CLR and asyn-

chronous DAC update (LDAC) pins are included.

The LTC2601/LTC2611/LTC2621 incorporate a power-on

reset circuit. During power-up, the voltage outputs rise

less than 10mV above zero scale until a valid write and

update take place. The power-on reset circuit resets the

LTC2601-1/LTC2611-1/LTC2621-1 to midscale. The volt-

age outputs stay at midscale until a valid write and update

take place.

■

Smallest Pin-Compatible Single DACs:

LTC2601: 16 Bits

LTC2611: 14 Bits

LTC2621: 12 Bits

■

Guaranteed Monotonic Over Temperature

■

Wide 2.5V to 5.5V Supply Range

■

Low Power Operation: 300µA at 3V

■

Power Down to 1µA, Max

■

High Rail-to-Rail Output Drive (±15mA, Min)

■

Double-Buffered Data Latches

■

Asynchronous DAC Update Pin

■

LTC2601-1/LTC2611-1/LTC2621-1: Power-On Reset

to Midscale

■

Tiny (3mm × 3mm) 10-Lead DFN Package

■

Mobile Communications

■

Process Control and Industrial Automation

■

Instrumentation

■

Automatic Test Equipment

Differential Nonlinearity (LTC2601)

APPLICATIO S

FEATURES

DESCRIPTIO

BLOCK DIAGRA

DAC

INPUT

32-BIT

SHIFT

12-/14-/16-BIT DAC

OUT

CONTROL

DECODE

LOGIC

LDAC

SDO

SDI

SCK

CS/LD

REF

GND

2601 BD

CLR

CODE

0 16384 32768 49152 65535

DNL (LSB)

2600 G02

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

= 5V

REF

= 4.096V

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 5396245

Summary of content (16 pages)

PAGE 1
LTC2601/LTC2611/LTC2621 16-/14-/12-Bit Rail-to-Rail DACs in 10-Lead DFN U FEATURES DESCRIPTIO ■ The LTC®2601/LTC2611/LTC2621 are single 16-, 14and 12-bit, 2.5V-to-5.5V rail-to-rail voltage output DACs in a 10-lead DFN package. They have built-in high performance output buffers and are guaranteed monotonic. Smallest Pin-Compatible Single DACs: LTC2601: 16 Bits LTC2611: 14 Bits LTC2621: 12 Bits Guaranteed Monotonic Over Temperature Wide 2.5V to 5.
PAGE 2
LTC2601/LTC2611/LTC2621 W W W AXI U U ABSOLUTE RATI GS (Note 1) Operating Temperature Range: LTC2601C/LTC2611C/LTC2621C LTC2601C-1/LTC2611C-1/LTC2621C-1 ... 0°C to 70°C LTC2601I/LTC2611I/LTC2621I LTC2601I-1/LTC2611I-1/LTC2621I-1 .. – 40°C to 85°C Any Pin to GND ........................................... – 0.3V to 6V Any Pin to VCC .............................................– 6V to 0.3V Maximum Junction Temperature ......................... 125°C Storage Temperature Range ................
PAGE 3
LTC2601/LTC2611/LTC2621 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.5V), VOUT unloaded, unless otherwise noted. SYMBOL GE PARAMETER Gain Error Gain Temperature Coefficient LTC2621/LTC2621-1 LTC2611/LTC2611-1 LTC2601/LTC2601-1 MIN TYP MAX MIN TYP MAX MIN TYP MAX ● ±0.03 ±0.7 ±0.1 ±0.7 ±0.05 ±0.
PAGE 4
LTC2601/LTC2611/LTC2621 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.5V), VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER LTC2621/LTC2621-1 LTC2611/LTC2611-1 LTC2601/LTC2601-1 MIN TYP MAX MIN TYP MAX MIN TYP MAX CONDITIONS UNITS AC Performance tS Settling Time (Note 6) ±0.024% (±1LSB at 12 Bits) ±0.006% (±1LSB at 14 Bits) ±0.
PAGE 5
LTC2601/LTC2611/LTC2621 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2601 Integral Nonlinearity (INL) 32 Differential Nonlinearity (DNL) 1.0 VCC = 5V VREF = 4.096V 24 INL vs Temperature 32 VCC = 5V VREF = 4.096V 0.8 VCC = 5V VREF = 4.096V 24 0.6 16 0.4 0 –8 0.2 INL (LSB) 8 DNL (LSB) INL (LSB) 16 0 –0.2 INL (POS) 8 0 –8 INL (NEG) –0.4 –16 –0.6 –24 –32 –16 –24 –0.8 0 16384 32768 CODE 49152 –1.
PAGE 6
LTC2601/LTC2611/LTC2621 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2611 Integral Nonlinearity (INL) 8 1.0 VCC = 5V VREF = 4.096V 6 Settling to ±1LSB Differential Nonlinearity (DNL) VCC = 5V VREF = 4.096V 0.8 0.6 4 0.4 DNL (LSB) INL (LSB) 2 0 –2 VOUT 100µV/DIV 0.2 0 CS/LD 2V/DIV –0.2 –0.4 8.9µs –4 –0.6 –6 –8 0 4096 8192 CODE 12288 –1.0 16383 2601 G11 2µs/DIV –0.8 0 4096 8192 CODE 12288 2601 G09 VCC = 5V, VREF = 4.
PAGE 7
LTC2601/LTC2611/LTC2621 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2601/LTC2611/LTC2621 Zero-Scale Error vs Temperature Gain Error vs Temperature 0.4 3 3 0.3 2.0 1.5 1.0 2 0.2 OFFSET ERROR (mV) GAIN ERROR (%FSR) 2.5 ZERO-SCALE ERROR (mV) Offset Error vs VCC 0.1 0 –0.1 0 –1 –0.2 0.5 –2 –0.3 0 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 –0.4 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 –3 2.5 90 3 3.5 4 VCC (V) 4.5 5 2601 G21 2601 G20 5.
PAGE 8
LTC2601/LTC2611/LTC2621 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2601/LTC2611/LTC2621 Supply Current vs Logic Voltage 1.4 VCC = 5V SWEEP SCK, SDI AND CS/LD 0V TO VCC 1.2 1.0 ICC (mA) Hardware CLR to Zero Scale Hardware CLR to Midscale VCC = 5V VREF = 4.096V CODE = FULL SCALE VCC = 5V VREF = 4.096V CODE = FULL SCALE VOUT 1V/DIV VOUT 1V/DIV 0.8 0.6 CLR 5V/DIV 0.4 CLR 5V/DIV 0.2 2601 G31 1µs/DIV 2601 G34 1µs/DIV 0 0 0.5 1 4.5 5 1.5 2 2.5 3 3.
PAGE 9
LTC2601/LTC2611/LTC2621 U U U PIN FUNCTIONS SDO (Pin 1): Serial Interface Data Output. The serial output of the shift register appears at the SDO pin. The data transferred to the device via the SDI pin is delayed 32 SCK rising edges before being output at the next falling edge. This pin is used for daisy-chain operation. CS/LD (Pin 5): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the register.
PAGE 10
LTC2601/LTC2611/LTC2621 W BLOCK DIAGRA 2 3 SDI 1 9 VCC SCK 32-BIT SHIFT REGISTER 5 6 REF INPUT REGISTER DAC REGISTER 12-/14-/16-BIT DAC VOUT 7 CS/LD CONTROL DECODE LOGIC SDO LDAC CLR 4 10 GND 8 2601 BD W UW TI I G DIAGRA S t1 t2 SCK t3 1 t6 t4 2 3 23 24 t10 SDI t5 t7 CS/LD t8 SDO t13 t12 LDAC 2601 F01a Figure 1a CS/LD t13 LDAC 2601 F01b Figure 1b 2601fa 10
PAGE 11
LTC2601/LTC2611/LTC2621 U OPERATIO Power-On Reset The LTC2601/LTC2611/LTC2621 clear the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. The LTC2601-1/ LTC2611-1/LTC2621-1 set the voltage outputs to midscale when power is first applied. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time.
PAGE 12
LTC2601/LTC2611/LTC2621 U OPERATIO INPUT WORD (LTC2601) COMMAND C3 C2 C1 C0 DON’T CARE BITS X X X X DATA (16 BITS) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB 2601 TBL01 INPUT WORD (LTC2611) COMMAND C3 C2 C1 C0 DON’T CARE BITS X X X X DATA (14 BITS + 2 DON’T CARE BITS) D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB X X LSB 2601 TBL02 INPUT WORD (LTC2621) COMMAND C3 C2 C1 C0 DON’T CARE BITS X X X X DATA (12 BITS + 4 DON’T CARE BITS) D11 D10 D9 D8 D
PAGE 13
LTC2601/LTC2611/LTC2621 U OPERATIO The DAC is powered up when LDAC is taken low, independent of the state of CS/LD. careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. If LDAC is low at the time CS/LD goes high, it inhibits any software power-down command that was specified in the input word. The PC board should have separate areas for the analog and digital sections of the circuit.
PAGE 14
X X SDI SDO SCK CS/LD 1 X X 2 X X 3 4 X 5 X X DON’T CARE X C3 SDI C2 2 C1 3 X X 6 X X 7 C0 X 6 X 7 4 DON’T CARE BITS X 5 X 8 D15 9 D14 10 D12 12 D11 13 D10 14 24-BIT INPUT WORD D13 11 D9 15 D7 17 DATA WORD D8 16 D6 18 C3 C3 C2 10 C1 11 C2 C1 COMMAND WORD 9 C0 C0 X 14 X 15 X X X 4 DON’T CARE BITS X 13 X X 16 17 D15 D15 PREVIOUS 32-BIT INPUT WORD 12 D14 D14 18 SDO SDI SCK D13 D13 19 D12 D12 20 t3 17 D10 D10 22 t2 t
PAGE 15
LTC2601/LTC2611/LTC2621 U OPERATIO POSITIVE FSE VREF = VCC VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) OUTPUT VOLTAGE 0 32, 768 INPUT CODE 2601 F03 65, 535 (a) 0V NEGATIVE OFFSET INPUT CODE (b) Figure 3. Effects of Rail-to-Rail Operation On the DAC Transfer Curve.
PAGE 16
LTC2601/LTC2611/LTC2621 U TYPICAL APPLICATIO Demo Circuit DC777 Schematic. Onboard 20-Bit ADC Measures Key Performance Parameters 5V 5V VREF 1V TO 5V 0.1µF 10 4 2 3 5 1 9 6 LDAC VCC VREF CLR SDI LTC2601 VOUT SCK CS/LD SDO GND SPI BUS 8 0.1µF 2 FSSET 7 100Ω 7.