Datasheet

LTC2497
8
2497fa
GND (Pins 1, 4, 6, 31, 32, 33, 34): Ground. Multiple
ground pins internally connected for optimum ground cur-
rent flow and V
CC
decoupling. Connect each one of these
pins to a common ground plane through a low impedance
connection. All seven pins must be connected to ground
for proper operation.
SCL (Pin 2): Serial Clock Pin of the I
2
C Interface. The
LTC2497 can only act as a slave and the SCL pin only ac-
cepts an external serial clock. Data is shifted into the SDA
pin on the rising edges of the SCL clock and output through
the SDA pin on the falling edges of the SCL clock.
SDA (Pin 3): Bidirectional Serial Data Line of the I
2
C
Interface. In the transmitter mode (Read), the conver-
sion result is output through the SDA pin, while in the
receiver mode (Write), the device channel select bits are
input through the SDA pin. The pin is high impedance
during the data input mode and is an open drain output
(requires an appropriate pull-up device to V
CC
) during the
data output mode.
NC (Pin 5): No Connect. This pin can be left floating or
tied to GND.
COM (Pin 7): The Common Negative Input (IN
–
) for All
Single-Ended Multiplexer Configurations. The voltage on
CH0-CH15 and COM pins can have any value between
GND – 0.3V to V
CC
+ 0.3V. Within these limits, the two
selected inputs (IN
+
and IN
–
) provide a bipolar input
range (V
IN
= IN
+
– IN
–
) from –0.5 • V
REF
to 0.5 • V
REF
.
Outside this input range, the converter produces unique
over-range and under-range output codes.
CH0 to CH15 (Pin 8-Pin 23): Analog Inputs. May be pro-
grammed for single-ended or differential mode.
MUXOUTP (Pin 24): Positive Multiplexer Output. Connect
to the input of external buffer/amplifier or short directly
to ADCINP.
ADCINP (Pin 25): Positive ADC Input. Connect to the
output of a buffer/amplifier driven by MUXOUTP or short
directly to MUXOUTP.
ADCINN (Pin 26): Negative ADC Input. Connect to the
output of a buffer/amplifier driven by MUXOUTN or short
directly to MUXOUTN
MUXOUTN (Pin 27): Negative Multiplexer Output. Con-
nect to the input of an external buffer/amplifier or short
directly to ADCINN.
V
CC
(Pin 28): Positive Supply Voltage. Bypass to GND with
a 10µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor as close to the part as possible.
REF
+
, REF
–
(Pin 29, Pin 30): Differential Reference Input.
The voltage on these pins can have any value between
GND and V
CC
as long as the reference positive input, REF
+
,
remains more positive than the negative reference input,
REF
–
, by at least 0.1V. The differential voltage (V
REF
= REF
+
– REF
–
) sets the full-scale range for all input channels.
f
O
(Pin 35): Frequency Control Pin. Digital input that
controls the internal conversion clock rate. When f
O
is
connected to GND, the converter uses its internal oscil-
lator running at 307.2kHz. The conversion clock may also
be overridden by driving the f
O
pin with an external clock
in order to change the output rate and the digital filter
rejection null.
CA0, CA1, CA2 (Pins 36, 37, 38): Chip Address Control
Pins. These pins are configured as a three-state (LOW,
HIGH, Floating) address control bits for the device I
2
C
address.
GND (Exposed Pad Pin 39): Ground. This pin is ground
and must be soldered to the PCB ground plane. For pro-
totyping purposes, this pin may remain floating.
pin FuncTions