Datasheet

LTC2496
22
2496fb
10µF
0.1µF
2.7V TO 5.5V
36
EOC
CS
SCK
(INTERNAL)
SDI
SDO
2496 F09
CONVERSION
DATA INPUT/OUTPUT
CONVERSION
1 0 EN SGL A2 A1 A0ODD
DON'T CAREDON'T CARE
MSBSIG“0”
V
CC
f
O
REF
+
REF
–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28 35
29
30
8
15
16
23
7
38
37
1,3,4,5,6,31,32,33,39
34
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2496
3-WIRE
SPI INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
OPTIONAL
10k
V
CC
2 31 4 5 6 7 8 9 19 20 21 22 23 24
LSB
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
applicaTions inForMaTion
Figure 9. Internal Serial Clock, Continuous Operation
The Use of a 10k Pull-Up on SCK for Internal SCK
Selection
If CS is pulled HIGH while the converter is driving SCK
LOW, the internal pull-up is not available to restore SCK
to a logic HIGH state if SCK is floating. This will cause the
device to exit the internal SCK mode on the next falling
edge of CS. This can be avoided by adding an external 10k
pull-up resistor to the SCK pin.
Whenever SCK is LOW, the LTC2496’s internal pull-up at
SCK is disabled. Normally, SCK is not externally driven if
the device is operating in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If the driver goes Hi-Z after outputting a
LOW signal, the internal pull-up is disabled. An external
10k pull-up resistor prevents the device from exiting the
internal SCK mode under this condition.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. If CS goes HIGH before the time t
EOCTEST
,
the internal pull-up is activated. If SCK is heavily loaded,
the internal pull-up may not restore SCK to a HIGH state
before the next falling edge of CS. The external 10k pull-up
resistor prevents the device from exiting the internal SCK
mode under this condition.
PRESERVING THE CONVERTER ACCURACY
The LTC2496 is designed to reduce as much as possible
sensitivity to device decoupling, PCB layout, anti-aliasing
circuits, line frequency perturbations, and temperature
sensitivity. In order to achieve maximum performance a
few simple precautions should be observed.
Digital Signal Levels
The LTC2496’s digital interface is easy to use. Its digital
inputs (SDI, f
O
, CS, and SCK in external serial clock mode)
accept standard CMOS logic levels. Internal hysteresis
circuits can tolerate edge transition times as slow as
100µs.