Datasheet

LTC2496
14
2496fb
applicaTions inForMaTion
Bit 20 (fourth output bit) is the most significant bit (MSB) of
the result. This bit in conjunction with Bit 21 also provides
under range and over range indication. If both Bit 21 and
Bit 20 are HIGH, the differential input voltage is above
+FS. If both Bit 21 and Bit 20 are LOW, the differential
input voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2496 Status Bits
Input Range Bit 23
EOC
Bit 22
DMY
Bit 21
SIG
Bit 20
MSB
V
IN
≥ 0.5 • V
REF
0 0 1 1
0V ≤ V
IN
< 0.5 • V
REF
0 0 1 0
–0.5 • V
REF
≤ V
IN
< 0V 0 0 0 1
V
IN
< –0.5 • V
REF
0 0 0 0
Bits 20 to 4 are the 16-bit plus sign conversion result
MSB first.
Bit 4 is the least significant bit (LSB
16
).
Bits 3 to 0 are always LOW.
Data is shifted out of the SDO pin under control of the
serial clock (SCK), see Figure 3. Whenever CS is HIGH,
SDO remains high impedance and SCK is ignored.
In order to shift the conversion result out of the device,
CS must first be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes in real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 23 (EOC) can be captured on the first
rising edge of SCK. Bit 22 is shifted out of the device on
the first falling edge of SCK. The final data bit (Bit 0) is
shifted out on the on the falling edge of the 23rd SCK and
may be latched on the rising edge of the 24th SCK pulse.
On the falling edge of the 24th SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (Bit 23) for the next conversion cycle.
Table 2 summarizes the output data format.
As long as the voltage on the IN
+
and IN
–
pins remains
between –0.3V and V
CC
+ 0.3V (absolute maximum op-
erating range) a conversion result is generated for any
differential input voltage V
IN
from –FS = –0.5 • V
REF
to
+FS = 0.5 • V
REF
. For differential input voltages greater
than +FS, the conversion result is clamped to the value
corresponding to +FS + 1LSB. For differential input volt-
ages below –FS, the conversion result is clamped to the
value –FS – 1LSB.
EOC
CS
SCK
(EXTERNAL)
SDI
SDO
2496 F03
CONVERSION
SLEEP
DATA INPUT/OUTPUT
CONVERSION
Hi-Z
Hi-Z
MSB LSB
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
SIG“0”
1 0 EN SGL A2 A1 A0ODD
BIT 18 BIT 17 BIT 16 BIT 15 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
1 2 3 4 5 6 7 8 9 19 20 21 22 23 24
DON'T CAREDON'T CARE
Figure 3. Channel Selection and Data Output Timing