LTC2496 16-Bit 8-/16-Channel ΔΣ ADC with Easy Drive Input Current Cancellation Features n n n n n n n n n n n n Description Up to 8 Differential or 16 Single-Ended Inputs Easy Drive Technology Enables Rail-to-Rail Inputs with Zero Differential Input Current Directly Digitizes High Impedance Sensors with Full Accuracy 600nV RMS Noise (0.
LTC2496 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) GND GND SDI fO CS SCK SDO TOP VIEW Supply Voltage (VCC).................................... –0.3V to 6V Analog Input Voltage (CH0 to CH15, COM)......................–0.3V to (VCC + 0.3V) Reference Input Voltage.................–0.3V to (VCC + 0.3V) ADCINN, ADCINP, MUXOUTP, MUXOUTN.....................................–0.3V to (VCC + 0.3V) Digital Input Voltage......................–0.3V to (VCC + 0.3V) Digital Output Voltage...........
LTC2496 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) PARAMETER CONDITIONS MIN TYP MAX UNITS Total Unadjusted Error 5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 15 15 15 ppm of VREF ppm of VREF ppm of VREF Output Noise 5.5V ≤ VCC ≤ 2.7V, 2.
LTC2496 Digital Inputs and Digital Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage (CS, fO, SDI) 2.7V ≤ VCC ≤ 5.5V (Note 18) l MIN VIL Low Level Input Voltage (CS, fO, SDI) 2.7V ≤ VCC ≤ 5.5V l VIH High Level Input Voltage (SCK) 2.7V ≤ VCC ≤ 5.5V (Notes 10, 15) l TYP MAX UNITS VCC – 0.5 V 0.5 V VCC – 0.
LTC2496 Digital Inputs and Digital Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
LTC2496 Typical Performance Characteristics –45°C 1 2 25°C 0 85°C –1 Integral Nonlinearity (VCC = 5V, VREF = 2.5V) 3 VCC = 5V VREF = 2.5V VIN(CM) = 1.25V fO = GND 1 2 INL (ppm OF VREF) 2 –45°C, 25°C, 90°C 0 –2 –1 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) 2 –3 –1.25 2.5 –0.75 4 12 8 85°C 25°C 0 TUE (ppm OF VREF) –45°C –4 Total Unadjusted Error (VCC = 5V, VREF = 2.5V) VCC = 5V VREF = 5V VIN(CM) = 1.25V fO = GND 85°C –45°C 0 –4 –12 –1.25 2.5 0.1 0 –0.75 –0.
LTC2496 Typical Performance Characteristics 0.1 0 –0.1 0 2 3 VREF (V) 308 306 304 2496 G28 –20 –40 –60 –80 On-Chip Oscillator Frequency vs VCC VREF = 2.5V VIN = 0V VIN(CM) = GND fO = GND TA = 25°C 306 304 302 0 15 30 45 60 TEMPERATURE (°C) 75 300 90 2.5 PSRR vs Frequency at VCC 0 VCC = 4.1V DC ±1.4V VREF = 2.5V IN+ = GND IN– = GND fO = GND TA = 25°C –60 –80 –120 –120 –140 2496 G31 2496 G32 Conversion Current vs Temperature 180 fO = GND CS = GND SCK = NC SDO = NC 2.
LTC2496 Pin Functions GND (Pins 1, 3, 4, 5, 6, 31, 32, 33): Ground. Multiple ground pins internally connected for optimum ground current flow and VCC decoupling. Connect each one of these pins to a common ground plane through a low impedance connection. All 8 pins must be connected to ground for proper operation. NC (Pin 2): No Connection, this pin can be left floating or tied to GND. COM (Pin 7): The common negative input (IN–) for all single-ended multiplexer configurations.
LTC2496 Functional Block Diagram INTERNAL OSCILLATOR VCC MUXOUTP ADCINP GND CH0 CH1 CH15 COM – • • • fO (INT/EXT) AUTOCALIBRATION AND CONTROL REF+ REF– + DIFFERENTIAL 3RD ORDER ∆∑ MODULATOR MUX SDI SCK SDO CS SERIAL INTERFACE DECIMATING FIR ADDRESS 2496 BD MUXOUTN ADCINN Figure 1. Functional Block Diagram Test Circuits SDO VCC 1.69k CLOAD = 20pF 1.
LTC2496 Timing Diagrams Timing Diagram Using Internal SCK (SCK HIGH with CS↓) CS t1 t2 SDO tKQMIN t3 tKQMAX SCK t7 t8 SDI 2496 TD01 SLEEP DATA IN/OUT CONVERSION Timing Diagram Using External SCK (SCK LOW with CS↓) CS t1 t2 SDO t5 SCK tKQMIN t6 t4 t7 tKQMAX t8 SDI 2496 TD02 SLEEP DATA IN/OUT CONVERSION 2496fb 10
LTC2496 Applications Information CONVERTER OPERATION The LTC2496 is a multi-channel, low power, delta-sigma analog-to-digital converter with an easy to use 4-wire interface and automatic differential input current cancellation. Its operation is made up of three states (See Figure 2). The converter operating cycle begins with the conversion, followed by the sleep state and ends with the data input/output cycle.
LTC2496 Applications Information front end. A proprietary front end passive sampling network transparently removes the differential input current. This enables external RC networks and high impedance sensors to directly interface to the LTC2496 without external amplifiers.
LTC2496 Applications Information In order to achieve optimum performance, if an external amplifier is not used, short these pins directly together (ADCINP to MUXOUTP and ADCINN to MUXOUTN) and minimize their capacitance to ground. Chip Select (CS) SERIAL INTERFACE PINS At the conclusion of a conversion cycle, while CS is HIGH, the device remains in a low power sleep state where the supply current is reduced several orders of magnitude.
LTC2496 Applications Information Bit 20 (fourth output bit) is the most significant bit (MSB) of the result. This bit in conjunction with Bit 21 also provides under range and over range indication. If both Bit 21 and Bit 20 are HIGH, the differential input voltage is above +FS. If both Bit 21 and Bit 20 are LOW, the differential input voltage is below –FS. The function of these bits is summarized in Table 1. In order to shift the conversion result out of the device, CS must first be driven LOW.
LTC2496 Applications Information Table 2. LTC2496 Output Data Format DIFFERENTIAL INPUT VOLTAGE VIN* BIT 23 EOC BIT 22 DMY BIT 21 SIG BIT 20 MSB BIT 19 BIT 18 BIT 17 … BIT 4 BITS 3 TO 0 VIN* ≥ FS** 0 0 1 1 0 0 0 … 0 0000 FS** – 1LSB 0 0 1 0 1 1 1 … 1 0000 0.5 • FS** 0 0 1 0 1 0 0 … 0 0000 0.5 • FS** – 1LSB 0 0 1 0 0 1 1 … 1 0000 0 0 0 1 0 0 0 0 … 0 0000 –1LSB 0 0 0 1 1 1 1 … 1 0000 –0.5 • FS** 0 0 0 1 1 0 0 … 0 0000 –0.
LTC2496 Applications Information Table 3.
LTC2496 Applications Information Table 4.
LTC2496 Applications Information When the device is in the sleep state, its conversion result is held in an internal static shift register. The device remains in the sleep state until the first rising edge of SCK is seen while CS is LOW. The input data is then shifted in via the SDI pin on each rising edge of SCK (including the first rising edge). The channel selection will be used for the following conversion cycle.
LTC2496 Applications Information External Serial Clock, 3-Wire I/O Since CS is tied LOW, the end-of-conversion (EOC) can be continuously monitored at the SDO pin during the convert and sleep states. EOC may be used as an interrupt to an external controller. EOC = 1 while the conversion is in progress and EOC = 0 once the conversion is complete. On the falling edge of EOC, the conversion result is loading into an internal static shift register.
LTC2496 Applications Information Internal Serial Clock, Single Cycle Operation When testing EOC, if the conversion is complete (EOC = 0), the device will exit sleep state. In order to return to the sleep state and reduce the power consumption, CS must be pulled HIGH before the device pulls SCK HIGH. When the device is using its own internal oscillator (fO is tied LOW), the first rising edge of SCK occurs 12µs (tEOCTEST = 12µs) after the falling edge of CS.
LTC2496 Applications Information Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH any time between the 1st rising edge and the 24th falling edge of SCK, see Figure 8. On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. In order to program a new input channel, 8 SCK clock pulses are required.
LTC2496 Applications Information 2.7V TO 5.5V 10µF 28 VCC fO = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 35 LTC2496 0.1µF 29 REFERENCE VOLTAGE 0.
LTC2496 Applications Information The digital input signal range is 0.5V to VCC – 0.5V. During transitions, the CMOS input circuits draw dynamic current. For optimal performance, application of signals to the serial data interface should be reserved for the sleep and data output periods. During the conversion period, overshoot and undershoot of fast digital signals applied to both the serial digital interface and the external oscillator pin (fO) may degrade the converter performance.
LTC2496 Applications Information When using the LTC2496’s internal oscillator, the input capacitor array is switched at 123kHz. The effect of the charge transfer depends on the circuitry driving the input/reference pins. If the total external RC time constant is less then 580ns the errors introduced by the sampling process are negligible since complete settling occurs. Typically, the reference inputs are driven from a low impedance source.
LTC2496 Applications Information Automatic Offset Calibration of External Buffers/ Amplifiers Reference Current The LTC6078 is an excellent amplifier for this function. It operates with supply voltages as low as 2.7V and its noise level is 18nV/√Hz. The Easy Drive input technology of the LTC2496 enables an RC network to be added directly to the output of the LTC6078.
LTC2496 Applications Information In cases where large bypass capacitors are required on the reference inputs (CREF > 0.01µF), full-scale and linearity errors are proportional to the value of the reference resistance. Every ohm of reference resistance produces a full-scale error of approximately 0.5ppm, see Figures 14 and 15. If the input common mode voltage is equal to the reference common mode voltage, a linearity error of approximately 0.67ppm per 100Ω of reference resistance results, see Figure 16.
LTC2496 Applications Information The user can expect to achieve this level of performance using the internal oscillator, as shown in Figure 19. Measured values of normal mode rejection are shown superimposed over the theoretical rejection. Traditional high order delta-sigma modulators suffer from potential instabilities at large input signal levels. The proprietary architecture used for the LTC2496 third order modulator resolves this problem and guarantees stability with input signals 150% of full-scale.
LTC2496 Applications Information continue to have zero differential input current, but the time required for complete settling (580ns for fEOSC = 307.2kHz) is reduced, proportionally. A change in fEOSC results in a proportional change in the internal notch position. This leads to reduced differential mode rejection of line frequencies.
LTC2496 Applications Information 22 24 VCC = VREF = 5V 20 20 VCC = 5V, VREF = 2.5V 18 16 VCC = 5V, VREF = 5V, 2.5V 14 VIN(CM) = VREF(CM) VIN = 0V fO = EXT CLOCK 12 T = 25°C A RES = LOG 2 (VREF/NOISERMS) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2496 F27 Figure 27. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Reference Voltage RESOLUTION (BITS) RESOLUTION (BITS) 22 18 16 VCC = VREF = 5V VCC = 5V, VREF = 2.
LTC2496 Package Description UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701 Rev C) 0.70 p 0.05 5.50 p 0.05 5.15 ± 0.05 4.10 p 0.05 3.00 REF 3.15 ± 0.05 PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 5.5 REF 6.10 p 0.05 7.50 p 0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 p 0.10 0.75 p 0.05 PIN 1 NOTCH R = 0.30 TYP OR 0.35 s 45o CHAMFER 3.00 REF 37 0.00 – 0.05 38 0.40 p0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2 5.15 ± 0.10 5.50 REF 7.
LTC2496 Revision History (Revision history begins at Rev B) REV DATE DESCRIPTION PAGE NUMBER B 7/10 Revised Typical Application drawing Added Note 18 1 4,5 2496fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2496 Typical Application External Buffers Provide High Impedance Inputs and Amplifier Offsets are Automatically Cancelled. LTC2496 ∆∑ ADC WITH EASY DRIVE INPUTS MUXOUTN INPUT MUX MUXOUTP ANALOG 17 INPUTS SDI SCK SDO CS 2 – 1/2 LT6078 3 + 6 – 5 1 1/2 LT6078 1k 0.1µF 7 1k 0.1µF + 2496 TA02 Related Parts PART NUMBER DESCRIPTION COMMENTS LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max Initial Accuracy, 5ppm/°C Drift LT1460 Micropower Series Reference 0.
