Datasheet

LTC2494
26
2494fd
applications inForMation
Figure 10. Internal Serial Clock, Reduced Data Output Length with Valid Channel and Configuration Selection
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC= 1 while the conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit sleep state. In order to return to the
sleep state and reduce the power consumption, CS must be
pulled HIGH before the device pulls SCK HIGH. When the
device is using its own internal oscillator (f
O
is tied LOW),
the first rising edge of SCK occurs 12µs (t
EOCTEST
= 12µs)
after the falling edge of CS. If f
O
is driven by an external
oscillator of frequency f
EOSC
, then t
EOCTEST
= 3.6/f
EOSC
.
If CS remains LOW longer than t
EOCTEST
, the first rising
edge of SCK will occur and the conversion result is shifted
out the SDO pin on the falling edge of SCK. The serial
input word (SDI) is shifted into the device on the rising
edge of SCK.
After the 24th rising edge of SCK a new conversion au-
tomatically begins. SDO goes HIGH (EOC = 1) and SCK
remains HIGH for the duration of the conversion cycle.
Once the conversion is complete, the cycle repeats.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing CS HIGH any time between the 1st rising edge and
the 24th falling edge of SCK (see Figure 10). On the ris-
ing edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge
of SCK, the new input channel is loaded and valid for the
next conversion cycle. If CS goes HIGH between the 8th
falling edge and the 16th falling edge of SCK, the new
channel is still loaded, but the converter configuration
Hi-Z
2494 F10
CS
SCK
(INTERNAL)
SDI
SDO
CONVERSION SLEEP DATA INPUT/OUTPUT
EOC
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11BIT 21BIT 22BIT 23 BIT 10 BIT 9 BIT 8 BIT 7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 0 EN SGL A2 A1 A0 EN2 IM FA FB SPD GS2 GS1 GS0ODD
DON'T CAREDON'T CARE
MSBSIG“0”
<t
EOCTEST
CONVERSION
10µF
0.1µF
2.7V TO 5.5V
V
CC
f
O
REF
+
REF
–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28 35
29
30
8
15
16
23
7
38
37
1,3,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2494
4-WIRE
SPI INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
OPTIONAL
10k
V
CC