Datasheet

LTC2494
22
2494fd
Figure 4. Internal PTAT Digital Output vs Temperature
Figure 5. Absolute Temperature Error
Table 6. LTC2494 Interface Timing Modes
CONFIGURATION
SCK
SOURCE
CONVERSION
CYCLE CONTROL
DATA OUTPUT
CONTROL
CONNECTION AND
WAVEFORMS
External SCK, Single Cycle
Conversion
External CS and SCK CS and SCK Figures 6, 7
External SCK, 3-Wire I/O External SCK SCK Figure 8
Internal SCK, Single Cycle
Conversion
Internal
CS↓ CS↓
Figures 9, 10
Internal SCK, 3-Wire I/O,
Continuous Conversion
Internal Continuous Internal Figure 11
SERIAL INTERFACE TIMING MODES
The LTC2494’s 4-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes
of operation. These include internal/external serial clock,
3- or 4-wire I/O, single cycle or continuous conversion. The
following sections describe each of these timing modes
in detail. In all cases, the converter can use the internal
oscillator (f
O
= LOW) or an external oscillator connected to
the f
O
pin. For each mode, the operating cycle, data input
format, data output format and performance remain the
same. Refer to Table 6 for a summary.
External Serial Clock, Single Cycle Operation
This timing mode uses an external serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 6).
The external serial clock mode is selected during the power-
up sequence and on each falling edge of CS. In order to
enter and remain in the external SCK mode of operation,
SCK must be driven LOW both at power-up and on each
CS falling edge. If SCK is HIGH on the falling edge of CS,
the device will switch to the internal SCK mode.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the conversion is complete and the device is in the sleep
state. Independent of CS, the device automatically enters
the sleep state once the conversion is complete; however,
in order to reduce the power, CS must be HIGH.
When the device is in the sleep state, its conversion result
is held in an internal static shift register. The device remains
in the sleep state until the first rising edge of SCK is seen
while CS is LOW. The input data is then shifted in via the
SDI pin on each rising edge of SCK (including the first rising
applications inForMation
TEMPERATURE (K)
0
DATAOUT
16
480
640
800
960
1020
400
2494 F04
320
0
300200100
160
V
CC
= 5V
V
REF
= 5V
SLOPE = 2.45 LSB
16
/K
TEMPERATURE (°C)
–55 –30 –5
ABSOLUTE ERROR (°C)
5
4
3
2
1
–4
–3
–2
–1
0
12095704520
2494 F05
–5