Datasheet

LTC2493
20
2493fd
S ACK DATA Sr DATA TRANSFERRING P
7-BIT ADDRESS
R/W
2493 F05
CONVERSION CONVERSIONSLEEP DATA INPUT/OUTPUT
Figure 6. Conversion Sequence
Initiating a New Conversion
When the LTC2493 finishes a conversion, it automatically
enters the sleep state. Once in the sleep state, the device is
ready for a read operation. After the device acknowledges
a read request, the device exits the sleep state and enters
the data output state. The data output state concludes
and the LTC2493 starts a new conversion once a STOP
condition is issued by the master or all 32 bits of data are
read out of the device.
During the data read cycle, a STOP command may be issued
by the master controller in order to start a new conversion
and abort the data transfer. This STOP command must be
issued during the ninth clock cycle of a byte read when
the bus is free (the ACK/NACK cycle).
LTC2493 Address
The LTC2493 has two address pins (CA0, CA1). Each may
be tied HIGH, LOW, or left floating enabling one of nine
possible addresses (see Table 5).
In addition to the configurable addresses listed in Table 5,
the LTC2493 also contains a global address (1110111)
which may be used for synchronizing multiple LTC2493s or
other LTC24XX delta-sigma I
2
C devices (see Synchronizing
Multiple LTC2493s with a Global Address Call section).
Operation Sequence
The LTC2493 acts as a transmitter or receiver, as shown
in Figure 6. The device may be programmed to perform
several functions. These include input channel selection,
measure the internal temperature, selecting the line fre-
quency rejection (50Hz, 60Hz, or simultaneous 50Hz and
60Hz) and a 2× speed mode.
Continuous Read
In applications where the input channel/configuration does
not need to change for each cycle, the conversion can be
continuously performed and read without a write cycle
(see Figure 7). The configuration/input channel remains
unchanged from the last value written into the device. If
the device has not been written to since power-up, the
configuration is set to the default value. At the end of a
read operation, a new conversion automatically begins.
At the conclusion of the conversion cycle, the next result
may be read using the method described above. If the
conversion cycle is not concluded and a valid address
selects the device, the LTC2493 generates a NACK signal
indicating the conversion cycle is in progress.
applicaTions inForMaTion
Table 5. Address Assignment
CA1 CA0 ADDRESS
LOW LOW 0010100
LOW HIGH 0010110
LOW Float 0010101
HIGH LOW 0100110
HIGH HIGH 0110100
HIGH Float 0100111
Float LOW 0010111
Float HIGH 0100101
Float Float 0100100