Datasheet

LTC2493
4
2493fd
i
2
c inpuTs anD DigiTal ouTpuTs
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at T
A
= 25°C. (Note 3)
analog inpuT anD reFerence
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IN
+
Absolute/Common Mode IN
+
Voltage
(IN
+
Corresponds to the Selected Positive Input Channel)
GND – 0.3V V
CC
+ 0.3V V
IN
–
Absolute/Common Mode IN
–
Voltage
(IN
–
Corresponds to the Selected Negative Input Channel)
GND – 0.3V V
CC
+ 0.3V V
V
IN
Input Differential Voltage Range (IN
+
– IN
–
)
l
–FS +FS V
FS Full-Scale of the Differential Input (IN
+
– IN
–
)
l
0.5V
REF
V
LSB Least Significant Bit of the Output Code
l
FS/2
24
REF
+
Absolute/Common Mode REF
+
Voltage
l
0.1 V
CC
V
REF
–
Absolute/Common Mode REF
–
Voltage
l
GND REF
+
– 0.1V V
V
REF
Reference Voltage Range (REF
+
– REF
–
)
l
0.1 V
CC
V
CS(IN
+
) IN
+
Sampling Capacitance 11 pF
CS(IN
–
) IN
–
Sampling Capacitance 11 pF
CS(V
REF
) V
REF
Sampling Capacitance 11 pF
I
DC_LEAK(IN
+
)
IN
+
DC Leakage Current Sleep Mode, IN
+
= GND
l
–10 1 10 nA
I
DC_LEAK(IN
–
)
IN
–
DC Leakage Current Sleep Mode, IN
–
= GND
l
–10 1 10 nA
I
DC_LEAK(REF
+
)
REF
+
DC Leakage Current Sleep Mode, REF
+
= V
CC
l
–100 1 100 nA
I
DC_LEAK(REF
–
)
REF
–
DC Leakage Current Sleep Mode, REF
–
= GND
l
–100 1 100 nA
t
OPEN
MUX Break-Before-Make 50 ns
QIRR MUX Off Isolation V
IN
= 2V
P-P
DC to 1.8MHz 120 dB
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage
l
0.7V
CC
V
V
IL
Low Level Input Voltage
l
0.3V
CC
V
V
IHA
Low Level Input Voltage for Address Pins CA0, CA1 and
Pin f
O
l
0.05V
CC
V
V
ILA
High Level Input Voltage for Address Pins CA0, CA1
l
0.95V
CC
V
R
INH
Resistance from CA0, CA1 to V
CC
to Set Chip Address
Bit to 1
l
10 kΩ
R
INL
Resistance from CA0, CA1 to GND to Set Chip Address
Bit to 0
l
10 kΩ
R
INF
Resistance from CA0, CA1 to GND or V
CC
to Set Chip
Address Bit to Float
l
2 MΩ
I
I
Digital Input Current (f
O
)
l
–10 10 µA
V
HYS
Hysteresis of Schmitt Trigger Inputs (Note 5)
l
0.05V
CC
V
V
OL
Low Level Output Voltage (SDA) I = 3mA
l
0.4 V
t
OF
Output Fall Time V
IH(MIN)
to V
IL(MAX)
Bus Load C
B
10pF to
400pF (Note 14)
l
20 + 0.1C
B
250 ns
I
IN
Input Leakage (SDA, SCL) 0.1V
CC
≤ V
IN
≤ 0.9V
CC
l
1 µA
C
CAX
External Capacitative Load On-Chip Address Pins (CA0,
CA1) for Valid Float
l
10 pF