Datasheet

LTC2489
13
2489fa
Figure 3a. Timing Diagram for Reading from the LTC2489
Figure 3b. Timing Diagram for Writing to the LTC2489
The first input bit (SGL) following the 101 sequence de-
termines if the input selection is differential (SGL = 0) or
single-ended (SGL = 1). For SGL = 0, two adjacent chan-
nels can be selected to form a differential input. For SGL
= 1, one of 4 channels is selected as the positive input.
The negative input is COM for all single-ended operations.
The remaining four bits (ODD, A2, A1, A0) determine
which channel(s) is/are selected and the polarity (for a
differential input).
Initiating a New Conversion
When the LTC2489 finishes a conversion, it automatically
enters the sleep state. Once in the sleep state, the device is
ready for a read operation. After the device acknowledges
a read request, the device exits the sleep state and enters
the data output state. The data output state concludes and
the LTC2489 starts a new conversion once a Stop condi-
tion is issued by the master or all 24 bits of data are read
out of the device.
During the data read cycle, a Stop command may be issued
by the master controller in order to start a new conversion
and abort the data transfer. This Stop command must be
issued during the ninth clock cycle of a byte read when
the bus is free (the ACK/NAK cycle).
LTC2489 Address
The LTC2489 has two address pins (CA0, CA1). Each may
be tied high, low, or left floating enabling one of 9 possible
addresses (see Table 4).
In addition to the configurable addresses listed in Table 4,
the LTC2489 also contains a global address (1110111)
which may be used for synchronizing multiple LTC2489s or
other LTC24XX delta-sigma I
2
C devices, (See Synchronizing
Multiple LTC2489s with Global Address Call section).
APPLICATIONS INFORMATION
SLEEP DATA OUTPUT
ACK BY
LTC2489
ACK BY
MASTER
ALWAYS LOW
START BY
MASTER
NAK BY
MASTER
LSBR MSBSIG
D23
7 … …89
1 2 9
1 2 3 4 5 6 7 8 9
1
7-BIT
ADDRESS
2489 F03a
SCL
SDA
ACK BY
LTC2489
ACK BY
LTC2489
NAK BY
LTC2489
START BY
MASTER
SGL ODD
W
01
SCL
SDA
EN A2 A1 A0
7…892
1 2 3 4 5 6 7 8 9
1
7-BIT ADDRESS
2489 F03b
XXXXXXXX
SLEEP DATA INPUT
19
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