Datasheet

LTC2486
24
2486fd
APPLICATIONS INFORMATION
remains HIGH for the duration of the conversion cycle.
Once the conversion is complete, the cycle repeats.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH any time between the 1st rising edge and the
32nd falling edge of SCK (see Figure 10). On the ris-
ing edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge of
SCK, the new input channel is loaded and valid for the next
conversion cycle. If CS goes high between the 8th falling
edge and the 16th falling edge of SCK, the new channel
is still loaded, but the converter confi guration remains
unchanged. In order to program both the input channel
and converter confi guration, CS must go high after the
16th falling edge of SCK (at this point all data has been
shifted into the device).
Internal Serial Clock, 3-Wire I/O, Continuous
Conversion.
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated
serial clock (SCK) signal (see Figure 11). In this case, CS is
permanently tied to ground, simplifying the user interface
or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 4ms after V
CC
exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the internal
serial clock timing mode is automatically selected if SCK
is fl oating or driven HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating
the conversion has fi nished and the device has entered
the sleep state. The device remains in the sleep state a
minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting and inputting data.
Figure 10. Internal Serial Clock, Reduced Data Output Length with Valid Channel and Confi guration Selection
Hi-Z
2486 F10
CS
SCK
(INTERNAL)
SDI
SDO
CONVERSION SLEEP DATA INPUT/OUTPUT
V
CC
f
O
SCK
SDI
GND
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2486
4-WIRE
SPI INTERFACE
EOC
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11BIT 21BIT 22BIT 23
BIT 10 BIT 9 BIT 8 BIT 7
1 2 3 4 5 6 7 8 9 10111213141516
1 0 EN SGL A2 A1 A0 EN2 IM FA FB SPD GS2 GS1 GS0ODD
DON'T CAREDON'T CARE
MSBSIG“0”
OPTIONAL
10k
V
CC
<t
EOCTEST
REF
+
REF
–
CH0
CH1
CH2
CH3
COM
12 1
13
14
8
9
10
11
7
3
4
6
5
2
2.7V TO 5.5V
0.1μF
10μF
CS
SDO
CONVERSION