Datasheet

LTC2485
16
2485fc
APPLICATIONS INFORMATION
Initiating a New Conversion
When the LTC2485 fi nishes a conversion, it automatically
enters the sleep state. Once in the sleep state, the device is
ready for a Read operation. After the device acknowledges
a Read request, the device exits the sleep state and enters
the data output state. The data output state concludes
and the LTC2485 starts a new conversion once a STOP
condition is issued by the master or all 32 bits of data are
read out of the device.
During the data read cycle, a stop command may be issued
by the master controller in order to start a new conversion
and abort the data transfer. This stop command must be
issued during the ninth clock cycle of a byte read when
the bus is free (the ACK/NAK cycle).
LTC2485 Address
The LTC2485 has two address pins, enabling one in 6
possible addresses, as shown in Table 4.
Table 4. LTC2485 Address Assignment
CA1 CA0/f
0
* ADDRESS
LOW HIGH 001 01 00
LOW Floating 001 01 01
Floating HIGH 001 01 11
Floating Floating 010 01 00
HIGH HIGH 010 01 10
HIGH Floating 010 01 11
* CA0/f
0
is treated as HIGH when driven by a valid external clock.
In addition to the confi gurable addresses listed in Table 4, the
LTC2485 also contains a global address (1110111) which
may be used for synchronizing multiple LTC2485s.
SLEEP DATA OUTPUT
START BY
MASTER
ACK BY
LTC2485
ACK BY SUB LSBs
MASTER
NAK BY
MASTER
LSBR MSBSGN D23
7 … …89 1 2 9
1 2 3 4 5 6 7 8 9
1
7-BIT
ADDRESS
2485 F04
Figure 4. Timing Diagram for Reading from the LTC2485