Datasheet

LTC2485
15
2485fc
APPLICATIONS INFORMATION
LTC2485 Data Format
After a START condition, the master sends a 7-bit address
followed by a R/W bit. The bit R/W is 1 for a Read request
and 0 for a Write request. If the 7-bit address agrees with
an LTC2485’s address, that device is selected. When the
device is in the conversion state, it does not accept the
request and issues a Not-Acknowledge (NAK) by leaving
SDA HIGH. A write operation will also generate an NAK
signal. If the conversion is complete, it issues an acknowl-
edge (ACK) by pulling SDA LOW.
The LTC2485 has two registers. The output register contains
the result of the last conversion and a user programmable
confi guration register that sets the converter operation
mode.
Th e output register contains the last conversion result.
After each conversion is completed, the device automati-
cally enters the sleep state where the supply current is
reduced to 1µA. When the LTC2485 is addressed for a
Read operation, it acknowledges (by pulling SDA LOW)
and acts as a transmitter. The master and receiver can read
up to four bytes from the LTC2485. After a complete Read
operation (4 bytes), the output register is emptied, a new
conversion is initiated, and a following Read request in the
same output phase will be NAKed. The LTC2485 output
data stream is 32 bits long, shifted out on the falling edges
of SCL. The fi rst bit is the conversion result sign bit (SIG),
(see Tables 2 and 3). This bit is HIGH if V
IN
≥ 0. It is LOW
if V
IN
<0. The second bit is the most signifi cant bit (MSB)
of the result.
The fi rst two bits (SIG and MSB) can be used
to
indicate over range conditions. If both bits are HIGH, the
differential input voltage is above +FS and the following 24
bits are set to LOW to indicate an overrange condition. If
both bits are LOW, the input voltage is below –FS and the
following 24 bits are set to HIGH to indicate an underrange
condition. The function of these two bits is summarized in
Table 1. The next 24 bits contain the conversion results in
binary two’s complement format. The remaining six bits
are Sub LSBs below the 24-bit level.
As long as the voltage on the IN
+
and IN
–
pins is main-
tained within the – 0.3V to (V
CC
+ 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage
V
IN
from –FS = –0.5 • V
REF
to
+FS=0.5 • V
REF
. For differential input voltages greater
than +FS, the conversion result is clamped to the value
corresponding to the +FS + 1LSB. For differential input
voltages below –FS, the conversion result is clamped to
the value corresponding to –FS – 1LSB.
Table 2. LTC2485 Status Bits
INPUT RANGE BIT 31 SIG BIT 30 MSB
V
IN
≥ 0.5 • V
REF
11
0V ≤ V
IN
< 0.5 • V
REF
1/0 0
–0.5 • V
REF
≤ V
IN
< 0V 0 1
V
IN
< –0.5 • V
REF
00
Table 3. LTC2485 Output Data Format
DIFFERENTIAL INPUT VOLTAGE V
IN
* BIT 31 SIG BIT 30 MSB BIT 29 BIT 28 BIT 27 … BIT 0
V
IN
* ≥ FS** 1 1 0 0 0 … 0
FS** – 1LSB 1 0 1 1 1 … 1
0.5 • FS** 1 0 1 0 0 … 0
0.5 • FS** – 1LSB 1 0 0 1 1 … 1
0 1/0*** 0 0 0 0 … 0
–1LSB 0 1 1 1 1 … 1
–0.5 • FS** 0 1 1 0 0 … 0
–0.5 • FS** – 1LSB 0 1 0 1 1 … 1
–FS** 0 1 0 0 0 … 0
V
IN
* < –FS** 0 0 1 1 1 … 1
*The differential input voltage V
IN
= IN
+
– IN
–
.
**The full-scale voltage FS = 0.5 • V
R0F
.
*** The sign bit changes state during the 0 output code when the device is operating in the 2x speed mode.