Datasheet

LTC2485
13
2485fc
APPLICATIONS INFORMATION
is an input only and the data line SDA is bidirectional. The
device supports the Standard-mode and the Fast-mode
for data transfer speeds up to 400kbit/s. Figure 2 shows
the defi nition of timing for Fast/Standard-mode devices
on the I
2
C-bus.
The START and STOP Conditions
A START condition is generated by transitioning SDA from
HIGH to LOW while SCL is HIGH. The bus is considered to
be busy after the START condition. When the data transfer
is fi nished, a STOP condition is generated by transitioning
SDA from LOW to HIGH while SCL is HIGH. The bus is free
again a certain time after the STOP condition. START and
STOP conditions are always generated by the master.
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The re-
peated START (Sr) conditions are functionally identical
to the START (S).
Data Transferring
After the START condition, the I
2
C bus is busy and data
transfer is set between a master and a slave. Data is trans-
ferred over I
2
C in groups of nine bits (one byte) followed
by an acknowledge bit, therefore each group takes nine
SCL cycles. The transmitter releases the SDA line during
the acknowledge clock pulse and the receiver issues an
Acknowledge (ACK) by pulling SDA LOW or leaves SDA
HIGH to indicate a Not Acknowledge (NAK) condition.
Change of data state can only happen while SCL is LOW.
Accessing the Special Features of the LTC2485
The LTC2485 combines a high resolution, low noise ∆Σ
analog-to-digital converter with an on-chip selectable
temperature sensor, programmable digital fi lter and output
rate control. These special features are selected through a
single 8-bit serial input word during the data input/output
cycle (see Figure 3).
SDA
SCL
SSrPS
t
f
t
LOW
t
HD;STA
t
HD;STA
t
BUF
t
SP
t
SU;STA
t
SU;STO
t
HD;DAT
t
HIGH
t
SU;DAT
t
r
t
r
t
r
2485 F02
Figure 2. Defi nition of Timing for F/S-Mode Devices on the I
2
C-Bus
SLEEP
DATA INPUT
ACK BY
LTC2485
START BY
MASTER
ACK BY
LTC2485
FA FB SPDIMW
2 … 7 8 9
1 2 3 4 5 6 7 8 9
1
7-BIT ADDRESS
2485 F03
SDA
SCL
Figure 3. Timing Diagram for Writing to the LTC2485