Datasheet

LTC2444/LTC2445/
LTC2448/LTC2449
18
2444589fc
For more information www.linear.com/LTC2444
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z
and BUSY monitored for the completion of a conversion.
As described above, CS may be pulled LOW at any time
in order to monitor the conversion status on the SDO pin.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing
CS HIGH anytime between the fifth falling edge and
the 32nd falling edge of SCK, see Figure 6. On the rising
edge of
CS , the device aborts the data output state and
immediately initiates a new conversion. Thirteen serial
input data bits are required in order to properly program
the speed/resolution and input channel. If the data output
sequence is aborted prior to the 13th rising edge of SCK,
the new input data is ignored, and the previously selected
speed/resolution and channel are used for the next conver-
sion cycle. This is useful for systems not requiring all 32
bits of output data, aborting an invalid conversion cycle or
synchronizing the start of a conversion. If a new channel
is being programmed, the rising edge of
CS must come
after the 14th falling edge of SCK in order to store the
data input sequence.
applicaTions inForMaTion
CS
SCK
(EXTERNAL)
SDI
SDO
BUSY
1 2 3 4 5 6 1 5
MSB
BIT 28 BIT 27 BIT 26 BIT 25
SIG
BIT 29
“0”
BIT 30
EOC
Hi-Z Hi-Z
BIT 31
2444589 F06
CONVERSION
SLEEP
SLEEP
DATA OUTPUT DATA OUTPUT
CONVERSION
CONVERSION
TEST EOC
DON'T CARE DON'T CARE
V
CC
F
O
REF
+
REF
–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28 35
29
30
8
15
16
23
7
38
37
1,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
2
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1µF
4.5V TO 5.5V
LTC2448
4-WIRE
SPI INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
BUSY
DON'T CARE
Figure 6. External Serial Clock, Reduced Output Data Length