Datasheet

LTC2440
11
2440fe
For more information www.linear.com/LTC2440
APPLICATIONS INFORMATION
Figure 3. Output Data Timing
the converter indicates the overrange or the underrange
condition using distinct output codes.
Output Data Format
The LTC2440 serial output data stream is 32-bits long.
The first 3-bits represent status information indicating
the sign and conversion state. The next 24-bits are the
conversion result, MSB first. The remaining 5-bits are
sub LSBs beyond the 24-bit level that may be included in
averaging or discarded without loss of resolution. In the
case of ultrahigh resolution modes, more than 24 effective
bits of performance are possible (see Table 3). Under these
conditions, sub LSBs are included in the conversion result
and represent useful information beyond the 24-bit level.
The third and fourth bit together are also used to indicate
an underrange condition (the differential input voltage is
below FS) or an overrange condition (the differential input
voltage is above +FS). For input conditions in excess of
twice full scale (|V
IN
| ≥ V
REF
), the converter may indicate
either overrange or underrange. Once the input returns to
the normal operating range, the conversion result is im
-
mediately accurate within the specifications of the device.
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign
indicator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0,
this bit is LOW.
Bit 28 (fourth output bit) is the most significant bit (MSB) of
the result. This bit in conjunction with Bit 29 also provides
the underrange or overrange indication. If both Bit 29 and
Bit 28 are HIGH, the differential input voltage is above +FS.
If both Bit 29 and Bit 28 are LOW, the differential input
voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2440 Status Bits
Input Range
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
V
IN
≥ 0.5 • V
REF
0 0 1 1
0V ≤ V
IN
< 0.5 • V
REF
0 0 1 0
–0.5 • V
REF
≤ V
IN
< 0V 0 0 0 1
V
IN
< –0.5 • V
REF
0 0 0 0
Bits ranging from 28 to 5 are the 24-bit conversion result
MSB first.
Bit 5 is the Least Significant Bit (LSB).
Bits ranging from 4 to 0 are sub LSBs below the 24-bit
level. Bits 4 to bit 0 may be included in averaging or dis
-
carded without loss of resolution.
Data is shifted out of the SDO pin under control of the
serial clock (SCK), see Figure 3. Whenever
CS
is HIGH,
SDO remains high impedance.
In order to shift the conversion result out of the device,
CS must first be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
rising edge of SCK. Bit 30 is shifted out of the device on
the first falling edge of SCK. The final data bit (Bit 0) is
MSBSIG“0”
1 2 3 4 5 26 27 32
BIT 0BIT 27 BIT 5
LSB
24
BIT 28BIT 29BIT 30
SDO
SCK
BUSY
CS
EOC
BIT 31
SLEEP DATA OUTPUT CONVERSION
2440 F03
Hi-Z
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.