Datasheet

LTC2433-1
13
24331fa
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2433-1 will abort any serial data
transfer in progress and start a new conversion cycle
anytime a LOW-to-HIGH transition is detected at the CS
pin after the converter has entered the data output state
(i.e., after the first rising edge of SCK occurs with
CS␣=␣LOW).
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by F
O
.
SERIAL INTERFACE TIMING MODES
The LTC2433-1’s 3-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes of
operation. These include internal/external serial clock,
2- or 3-wire I/O, single cycle conversion and autostart. The
following sections describe each of these serial interface
timing modes in detail. In all these cases, the converter
can use the internal oscillator (F
O
= LOW) or an external
oscillator connected to the F
O
pin. Refer to Table␣ 4 for a
summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 6.
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.
Figure 6. External Serial Clock, Single Cycle Operation
Table 4. LTC2433-1 Interface Timing Modes
Conversion Data Connection
SCK Cycle Output and
Configuration Source Control Control Waveforms
External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 6, 7
External SCK, 2-Wire I/O External SCK SCK Figure 8
Internal SCK, Single Cycle Conversion Internal CS ↓ CS ↓ Figures 9, 10
Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 11
EOC
BIT 18
SDO
SCK
(EXTERNAL)
CS
TEST EOC
MSBSIG“O”
BIT 0
LSB
BIT 2 BIT 1BIT 14 BIT 13BIT 15BIT 16BIT 17
SLEEP
SLEEP
TEST EOC
(OPTIONAL)
DATA OUTPUT CONVERSION
24331 F06
CONVERSION
Hi-ZHi-ZHi-Z
TEST EOC
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
V
CC
F
O
REF
+
REF
–
SCK
IN
+
IN
–
SDO
GND
CS
110
2
3
9
4
5
8
6
7
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
1µF
2.7V TO 5.5V
LTC2433-1
3-WIRE
SPI INTERFACE
APPLICATIO S I FOR ATIO
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