Datasheet

8
LTC2420
TYPICAL PERFOR A CE CHARACTERISTICS
UW
INL vs Output Rate INL vs Output Rate Resolution vs Output Rate
OUTPUT RATE (Hz)
0 7.5
RESOLUTION (BITS)
20
22
75
2420 G30
18
16
25
50
100
24
T
A
= 25°C
T
A
= 90°C
T
A
= –45°C
V
CC
= 5V
V
REF
= 5V
f
O
= EXTERNAL
V
CC
(Pin 1): Positive Supply Voltage. Bypass to GND
(Pin␣ 4) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
V
REF
(Pin 2): Reference Input. The reference voltage range
is 0.1V to V
CC
.
V
IN
(Pin 3): Analog Input. The input voltage range is
–0.125 • V
REF
to 1.125 • V
REF
. For V
REF
> 2.5V the input
voltage range may be limited by the pin absolute maxi-
mum rating of –0.3V to V
CC
+ 0.3V.
GND (Pin 4): Ground. Shared pin for analog ground,
digital ground, reference ground and signal ground. Should
be connected directly to a ground plane through a mini-
mum length trace or it should be the single-point-ground
in a single point grounding system.
CS (Pin 5): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW on CS wakes up the ADC. A
LOW-to-HIGH transition on this pin disables the SDO
digital output. A LOW-to-HIGH transition on CS during the
Data Output transfer aborts the data transfer and starts a
new conversion.
SDO (Pin 6): Three-State Digital Output. During the data
output period this pin is used for serial data output. When
the chip select CS is HIGH (CS = V
CC
), the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin can be used as a conversion status out-
put. The conversion status can be observed by pulling CS
LOW.
SCK (Pin 7): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the data output
period. In External Serial Clock Operation mode, SCK is
used as digital input for the external serial interface. A
weak internal pull-up is automatically activated in Internal
Serial Clock Operation mode. The Serial Clock mode is
determined by the level applied to SCK at power up and the
falling edge of CS.
F
O
(Pin 8): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the F
O
pin is connected to V
CC
(F
O
= V
CC
), the
converter uses its internal oscillator and the digital filter’s
first null is located at 50Hz. When the F
O
pin is connected
to GND (F
O
= OV), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When F
O
is driven by an external clock signal with a frequency f
EOSC
,
the converter uses this signal as its clock and the digital
filter first null is located at a frequency f
EOSC
/2560.
PIN FUNCTIONS
UU
U
OUTPUT RATE (Hz)
0
TUE RESOLUTION (BITS)
16
18
20
40
2420 G28
14
12
10
10
20
30
50 60 70 80 90
100
V
CC
= 5V
V
REF
= 5V
F
O
= EXTERNAL
T
A
= –45°C
T
A
= 25°C
T
A
= 90°C
OUTPUT RATE (Hz)
0
TUE RESOLUTION (BITS)
16
18
20
40
2420 G29
14
12
10
10
20
30
50 60 70 80 90
100
V
CC
= 3V
V
REF
= 2.5V
F
O
= EXTERNAL
T
A
= –45°C
T
A
= 25°C
T
A
= 90°C