Datasheet

21
LTC2420
APPLICATIO S I FOR ATIO
WUU
U
capacitor tied to CS, see Figure 12. The time the converter
spends in the sleep state is determined by the value of the
external timing capacitor, see Figures 13 and 14. Once the
voltage at CS falls below an internal threshold (≈1.4V), the
device automatically begins outputting data. The data
output cycle begins on the first rising edge of SCK and
ends on the 24th rising edge. Data is shifted out the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
After the 24th rising edge, CS is pulled HIGH and a new
conversion is immediately started. This is useful in appli-
cations requiring periodic monitoring and ultralow power.
Figure 15 shows the average supply current as a function
of capacitance on CS.
It should be noticed that the external capacitor discharge
current is kept very small in order to decrease the con-
verter power dissipation in the sleep state. In the autostart
mode the analog voltage on the CS pin cannot be observed
without disturbing the converter operation using a regular
oscilloscope probe. When using this configuration, it is
important to minimize the external leakage current at the
CS pin by using a low leakage external capacitor and
properly cleaning the PCB surface.
SDO
Hi-ZHi-Z
SCK
(INTERNAL)
CS
V
CC
GND
2420 F12
V
CC
F
O
V
REF
SCK
V
IN
SDO
GND
C
EXT
CS
V
REF
0.1V TO V
CC
V
IN
–0.12V
REF
TO 1.12V
REF
1µF
2.7V TO 5.5V
LTC2420
BIT 0
SIG
BIT 21BIT 22
SLEEP
DATA OUTPUT CONVERSIONCONVERSION
EOC
BIT 23
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
Figure 12. Internal Serial Clock, Autostart Operation
CAPACITANCE ON CS (pF)
1
5
6
7
1000 10000
2420 F13
4
3
10 100 100000
2
1
0
t
SAMPLE
(SEC)
V
CC
= 5V
V
CC
= 3V
Figure 13. CS Capacitance vs f
SAMPLE