Datasheet

19
LTC2420
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 24th rising edge of SCK. After the
24th rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH, and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 24th rising edge of
SCK, see Figure 10. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 24 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2420’s internal pull-up at
pin SCK is disabled. Normally, SCK is not externally driven
if the device is in the internal SCK timing mode. However,
certain applications may require an external driver on SCK.
If this driver goes Hi-Z after outputting a LOW signal, the
LTC2420’s internal pull-up remains disabled. Hence, SCK
remains LOW. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external 10k pull-up resistor to SCK, this pin goes HIGH
once the external driver goes Hi-Z. On the next CS falling
edge, the device will remain in the internal SCK timing
mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0), SCK
will go LOW. Once CS goes HIGH (within the time period
defined above as t
EOCtest
), the internal pull-up is activated.
For a heavy capacitive load on the SCK pin, the internal
pull-up may not be adequate to return SCK to a HIGH level
before CS goes low again. This is not a concern under
normal conditions where CS remains LOW after detecting
EOC = 0. This situation is easily overcome by adding an
external 10k pull-up resistor to the SCK pin.
APPLICATIO S I FOR ATIO
WUU
U
SDO
SCK
(INTERNAL)
CS
>t
EOCtest
MSBEXRSIG
BIT 8
TEST EOCTEST EOC
BIT 19 BIT 18BIT 20BIT 21BIT 22
EOC
BIT 23
EOC
BIT 0
SLEEP DATA OUTPUT
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
DATA OUTPUT
CONVERSIONCONVERSIONSLEEP
2420 F10
<t
EOCtest
V
CC
F
O
V
REF
SCK
V
IN
SDO
GND CS
V
REF
0.1V TO V
CC
V
IN
–0.12V
REF
TO 1.12V
REF
1µF
2.7V TO 5.5V
LTC2420
V
CC
10k
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
TEST EOC
Figure 10. Internal Serial Clock, Reduced Data Output Length