Datasheet

LTC2415/LTC2415-1
29
sn2415 24151fs
APPLICATIO S I FOR ATIO
WUU
U
Figure 22. +FS Error vs R
SOURCE
at IN
+
or IN
–
(Large C
IN
)
Figure 23. –FS Error vs R
SOURCE
at IN
+
or IN
–
(Large C
IN
)
Figure 24. Offset Error vs Common Mode Voltage
(V
INCM
= IN
+
= IN
–
) and Input Source Resistance Imbalance
(∆R
IN
= R
SOURCEIN
+ – R
SOURCEIN
–) for Large C
IN
Values (C
IN
≥ 1µF)
R
SOURCE
(Ω)
0
100 200 300 400 500 600 700 800 9001000
+FS ERROR (ppm OF V
REF
)
2415 F22
300
240
180
120
60
0
V
CC
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= 3.75V
IN
–
= 1.25V
F
O
= GND
T
A
= 25°C
C
IN
= 0.01µF
C
IN
= 0.1µF
C
IN
= 1µF, 10µF
R
SOURCE
(Ω)
0
100 200 300 400 500 600 700 800 9001000
–FS ERROR (ppm OF V
REF
)
2415 F23
0
–60
–120
–180
–240
–300
V
CC
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= 1.25V
IN
–
= 3.75V
F
O
= GND
T
A
= 25°C
C
IN
= 0.01µF
C
IN
= 0.1µF
C
IN
= 1µF, 10µF
V
INCM
(V)
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
OFFSET ERROR (ppm OF V
REF
)
2415 F24
120
100
80
60
40
20
0
–20
–40
–60
–80
–100
–120
F
O
= GND
T
A
= 25°C
R
SOURCEIN
– = 500Ω
C
IN
= 10µF
V
CC
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= IN
–
= V
INCM
A: ∆R
IN
= +400Ω
B: ∆R
IN
= +200Ω
C: ∆R
IN
= +100Ω
D: ∆R
IN
= 0Ω
E: ∆R
IN
= –100Ω
F: ∆R
IN
= –200Ω
G: ∆R
IN
= –400Ω
A
B
C
D
E
F
G
used for the external source impedance seen by IN
+
and
IN
–
, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 100Ω source resistance will create
a 0.1µV typical and 1µV maximum offset voltage.