Datasheet

LTC2415/LTC2415-1
27
sn2415 24151fs
APPLICATIO S I FOR ATIO
WUU
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Figure 18. LTC2415/LTC2415-1 Equivalent Analog Input Circuit
Figure 19. An RC Network at IN
+
and IN
–
Figure 21. –FS Error vs R
SOURCE
at IN
+
or IN
–
(Small C
IN
)
Figure 20. +FS Error vs R
SOURCE
at IN
+
or IN
–
(Small C
IN
)
IIN
VV V
R
IIN
VV V
R
I REF
VV V
R
V
VR
I REF
VV V
R
V
VR
where
AVG
IN INCM REFCM
EQ
AVG
IN INCM REFCM
EQ
AVG
REF INCM REFCM
EQ
IN
REF EQ
AVG
REF INCM REFCM
EQ
IN
REF EQ
+
−
+
−
()
=
+−
•
()
=
−+ −
•
()
=
•− +
•
−
•
()
=
−• − +
•
+
•
05
05
15
05
15
05
2
2
.
.
.
.
.
.
::
.
.
./
.
V REF REF
V
REF REF
VININ
V
IN IN
R M INTERNAL OSCILLATOR Hz Notch F LOW
R M INTERNAL OSCILLATOR Hz Notch F HIGH
R f EXTERNAL OSCILLATOR
R
REF
REFCM
IN
INCM
EQ O
EQ O
EQ EOSC
EQ
=−
=
+






=−
=
−






==
()
==
()
=•
()
=
+−
+−
+−
+−
2
2
361 60
432 50
0 555 10
397
12
Ω
Ω
LTC2415
LTC2415
MM INTERNAL OSCILLATOR Hz Hz Notch F LOW
O
Ω 50 60/ =
()
LTC2415-1
C
IN
2415 F19
V
INCM
+ 0.5V
IN
R
SOURCE
IN
+
LTC2415/
LTC2415-1
C
PAR
≅20pF
C
IN
V
INCM
– 0.5V
IN
R
SOURCE
IN
–
C
PAR
≅20pF
R
SOURCE
(Ω)
1 10 100 1k 10k 100k
+FS ERROR (ppm OF V
REF
)
2415 F20
50
40
30
20
10
0
V
CC
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= 5V
IN
–
= 2.5V
F
O
= GND
T
A
= 25°C
C
IN
= 0.01µF
C
IN
= 0.001µF
C
IN
= 100pF
C
IN
= 0pF
R
SOURCE
(Ω)
1 10 100 1k 10k 100k
–FS ERROR (ppm OF V
REF
)
2415 F21
0
–10
–20
–30
–40
–50
V
CC
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= GND
IN
–
= 2.5V
F
O
= GND
T
A
= 25°C
C
IN
= 0.01µF
C
IN
= 0.001µF
C
IN
= 100pF
C
IN
= 0pF
V
REF
+
V
IN
+
V
CC
R
SW
(TYP)
20k
I
LEAK
I
LEAK
V
CC
I
LEAK
I
LEAK
V
CC
R
SW
(TYP)
20k
C
EQ
18pF
(TYP)
R
SW
(TYP)
20k
I
LEAK
I
IN
+
V
IN
–
I
IN
–
I
REF
+
I
REF
–
2415 F18
I
LEAK
V
CC
I
LEAK
I
LEAK
SWITCHING FREQUENCY
f
SW
= 76800Hz INTERNAL
OSCILLATOR (LTC2415)
(F
O
= LOW OR HIGH)
f
SW
= 69900Hz INTERNAL
OSCILLATOR (LTC2415-1)
(F
O
= LOW)
f
SW
= 0.5 • f
EOSC
EXTERNAL OSCILLATOR
V
REF
–
R
SW
(TYP)
20k
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 18 shows the
mathematical expressions for the average bias currents
flowing through the IN
+
and IN
–
pins as a result of the
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 19. The C
PAR
capacitor
includes the LTC2415/LTC2415-1 pin capacitance (5pF
typical) plus the capacitance of the test fixture used to
obtain the results shown in Figures 20 and 21. A careful
implementation can bring the total input capacitance (C
IN
+ C
PAR
) closer to 5pF thus achieving better performance
than the one predicted by Figures 20 and 21. For simplic-
ity, two distinct situations can be considered.