Datasheet

LTC2415/LTC2415-1
22
sn2415 24151fs
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2415/LTC2415-1 internal
pull-up at pin SCK is disabled. Normally, SCK is not
externally driven if the device is in the internal SCK timing
mode. However, certain applications may require an exter-
nal driver on SCK. If this driver goes Hi-Z after outputting
a LOW signal, the LTC2415/LTC2415-1 internal pull-up
remains disabled. Hence, SCK remains LOW. On the next
falling edge of CS, the device is switched to the external
SCK timing mode. By adding an external 10k pull-up
resistor to SCK, this pin goes HIGH once the external driver
goes Hi-Z. On the next CS falling edge, the device will
remain in the internal SCK timing mode.
APPLICATIO S I FOR ATIO
WUU
U
Figure 12. Internal Serial Clock, Reduced Data Output Length
SDO
SCK
(INTERNAL)
CS
>t
EOCtest
MSBSIG
BIT 8
TEST EOCTEST EOC
BIT 27 BIT 26BIT 28BIT 29BIT 30
EOC
BIT 31
EOC
BIT 0
SLEEP DATA OUTPUT
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
DATA OUTPUT
CONVERSIONCONVERSIONSLEEP
2415 F12
<t
EOCtest
V
CC
10k
TEST EOC
V
CC
F
O
REF
+
REF
–
SCK
IN
+
IN
–
SDO
GND
CS
214
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
3-WIRE
SPI INTERFACE
1µF
2.7V TO 5.5V
LTC2415/
LTC2415-1
= 50Hz REJECTION (LTC2415)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2415)
= 50Hz/60Hz REJECTION (LTC2415-1)
V
CC
by an external oscillator of (LTC2415-1) frequency f
EOSC
,
then t
EOCtest
is 3.6/f
EOSC
. If CS is pulled HIGH before time
t
EOCtest
, the device remains in the sleep state. The conver-
sion result is held in the internal static shift register.
If CS remains LOW longer than t
EOCtest
, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 12. On the rising edge of CS, the device
aborts the data output state and immediately initiates a