LTC2415/LTC2415-1 24-Bit No Latency ∆ΣTM ADCs with Differential Input and Differential Reference DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2× × Speed Up Version of the LTC2410/LTC2413: 15Hz Output Rate, 50Hz or 60Hz Notch—LTC2415; 13.75Hz Output Rate, Simultaneous 50Hz/60Hz Notch—LTC2415-1 Differential Input and Differential Reference with GND to VCC Common Mode Range 2ppm INL, No Missing Codes 2.5ppm Gain Error 0.
LTC2415/LTC2415-1 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Notes 1, 2) Supply Voltage (VCC) to GND .......................– 0.3V to 7V Analog Input Pins Voltage to GND .................................... – 0.3V to (VCC + 0.3V) Reference Input Pins Voltage to GND .................................... – 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.
LTC2415/LTC2415-1 U CO VERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) PARAMETER CONDITIONS MIN ≤ REF+ ≤ TYP MAX UNITS 2.5V VCC, REF– = GND, – GND ≤ IN = IN+ ≤ VCC, (Note 7) 2.
LTC2415/LTC2415-1 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN VIH High Level Input Voltage CS, FO 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 3.3V ● VIL Low Level Input Voltage CS, FO 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V ● VIH High Level Input Voltage SCK 2.7V ≤ VCC ≤ 5.5V (Note 9) 2.7V ≤ VCC ≤ 3.
LTC2415/LTC2415-1 UW TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN fEOSC External Oscillator Frequency Range ● tHEO External Oscillator High Period ● tLEO External Oscillator Low Period tCONV Conversion Time (LTC2415) MAX UNITS 2.56 2000 kHz 0.25 390 µs ● 0.25 390 µs FO = 0V FO = VCC External Oscillator (Note 11) ● ● ● 65.43 78.
LTC2415/LTC2415-1 U W TYPICAL PERFOR A CE CHARACTERISTICS Total Unadjusted Error Over Temperature (VCC = 5V, VREF = 5V) 105.5 TA = 25°C 105.0 104.5 125 213 121 TA = 90°C 211 209 VCC = 5V VREF = 2.5V VINCM = 1.25V REF + = 2.5V REF – = GND FO = GND 207 TA = –45°C 104.0 215 103.5 –2.5 –2 –1.5 –1 –0.5 0 0.5 VIN (V) 1 1.5 2 205 –1.25 2.5 TUE (ppm OF VREF) TUE (ppm OF VREF) 106.0 TUE (ppm OF VREF) VCC = 5V VREF = 5V VINCM = 2.5V REF + = 5V REF – = GND FO = GND TA = 90°C –0.
LTC2415/LTC2415-1 U W TYPICAL PERFOR A CE CHARACTERISTICS 6 4 10 8 6 4 10,000 CONSECUTIVE READINGS VCC = 5V VREF = 2.5V VIN = 0V REF + = 2.5V REF – = GND IN + = 1.25V IN – = 1.25V FO = 460800Hz TA = 25°C 2 2 0 –212 –210.5 –209 –207.5 OUTPUT CODE (ppm OF VREF) 0 –211.5 –206 –210.5 –209.5 –208.5 OUTPUT CODE (ppm OF VREF) Noise Histogram (Output Rate = 15Hz, VCC = 2.7V, VREF = 2.5V) 8 6 4 10 GAUSSIAN DISTRIBUTION m = –113.1ppm σ = 0.59ppm 2 0 –116 –114.5 –113 –111.
LTC2415/LTC2415-1 U W TYPICAL PERFOR A CE CHARACTERISTICS RMS Noise vs VINCM RMS Noise vs Temperature (TA) 1800 IN + = VINCM IN – = VINCM FO = GND TA = 25°C 1520 1250 1400 1480 1100 1200 VCC = 5V VIN = 0V REF + = 5V REF – = GND IN + = 2.5V IN – = 2.5V FO = GND 950 1000 –0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VINCM (V) 800 –50 –25 0 25 50 TEMPERATURE (°C) 75 2415 G19 RMS Noise vs VREF 1320 VCC = 5V REF – = GND IN + = GND IN – = GND FO = GND TA = 25°C 800 1 1.5 2 2.5 3 VREF (V) 3.
LTC2415/LTC2415-1 U W TYPICAL PERFOR A CE CHARACTERISTICS +Full-Scale Error vs VCC 5 0 4 3 2 1 0 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 – FULL-SCALE ERROR (ppm OF VREF) 8 VREF = 2.5V REF + = 2.5V REF – = GND IN + = 1.25V IN – = GND FO = GND TA = 25°C + FULL-SCALE ERROR (ppm OF VREF) 4 0 VCC = 5V REF + = VREF REF – = GND IN + = 0.5 • REF + IN – = GND FO = GND TA = 25°C –4 0.5 1 1.5 2 2.5 3 3.5 VREF (V) 4 2415 G28 –1 –2 VREF = 2.5V REF + = 2.5V REF – = GND IN + = GND IN – = 1.
LTC2415/LTC2415-1 U W TYPICAL PERFOR A CE CHARACTERISTICS Conversion Current vs Output Data Rate Sleep Current vs Temperature (TA) 1000 25 SUPPLY CURRENT (µA) 800 700 600 500 400 SUPPLY CURRENT (µA) VCC = 5V REF + = 5V REF – = GND IN + = GND IN – = GND FO = EXT OSC CS = GND SCK =N/C SDO = N/C 900 300 + 24 VREF– = VCC VREF = GND 23 VIN+ = VIN– = GND FO = GND 22 CS = V CC 21 SCK = SDO = N/C 19 18 200 17 100 16 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2415 G37 VCC =
LTC2415/LTC2415-1 U U U PI FU CTIO S FO (Pin 14): Frequency Control Pin. Digital input that controls the ADC’s notch frequencies and conversion time. When the FO pin is connected to VCC (LTC2415 only), the converter uses its internal oscillator and the digital filter first null is located at 50Hz. When the FO pin is connected to GND (FO = OV), the converter uses its internal oscillator and the digital filter first null is located at 60Hz (LTC2415) or simultaneous 50Hz/60Hz (LTC2415-1).
LTC2415/LTC2415-1 U U W U APPLICATIO S I FOR ATIO CONVERTER OPERATION Converter Operation Cycle The LTC2415/LTC2415-1 are low power, delta-sigma analog-to-digital converters with an easy to use 3-wire serial interface (see Figure 1). Their operation is made up of three states. The converter operating cycle begins with the conversion, followed by the sleep state and ends with the data output (see Figure 2).
LTC2415/LTC2415-1 U W U U APPLICATIO S I FOR ATIO The LTC2415/LTC2415-1 perform a full-scale calibration every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of full-scale readings with respect to time, supply voltage change and temperature drift. Unlike the LTC2410 and LTC2413, the LTC2415 and LTC2415-1 do not perform an offset calibration every conversion cycle.
LTC2415/LTC2415-1 U U W U APPLICATIO S I FOR ATIO Output Data Format The LTC2415/LTC2415-1 serial output data stream is 32 bits long. The first 3 bits represent status information indicating the sign and conversion state. The next 24 bits are the conversion result, MSB first. The remaining 5 bits are sub LSBs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution.
LTC2415/LTC2415-1 U U W U APPLICATIO S I FOR ATIO While the variation in offset with supply voltage is proportional to VCC (see Figure 4), several characteristics of this variation can be used to eliminate the effects. First, the variation with respect to supply voltage is linear. Second, the magnitude of the offset error decreases with decreased supply voltage. Third, the offset error increases with increased reference voltage with an equal and opposite magnitude to the supply voltage variation.
LTC2415/LTC2415-1 U W U U APPLICATIO S I FOR ATIO Frequency Rejection Selection LTC2415 (FO) The LTC2415 internal oscillator provides better than 110dB normal mode rejection at the line frequency and its harmonics for 50Hz ±2% or 60Hz ±2%. For 60Hz rejection, FO should be connected to GND while for 50Hz rejection the FO pin should be connected to VCC. The selection of 50Hz or 60Hz rejection can also be made by driving FO to an appropriate logic level.
LTC2415/LTC2415-1 U U W U APPLICATIO S I FOR ATIO state and the converter is in the Internal SCK mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. Table 3b summarizes the duration of each state and the achievable output data rate as a function of FO. The LTC2415/LTC2415-1 transmit the conversion results and receive the start of conversion command through a synchronous 3-wire interface.
LTC2415/LTC2415-1 U W U U APPLICATIO S I FOR ATIO Serial Clock Input/Output (SCK) The serial clock signal present on SCK (Pin 13) is used to synchronize the data transfer. Each bit of data is shifted out the SDO pin on the falling edge of the serial clock. In the Internal SCK mode of operation, the SCK pin is an output and the LTC2415/LTC2415-1 create their own serial clock by dividing the internal conversion clock by 8. In the External SCK mode of operation, the SCK pin is used as input.
LTC2415/LTC2415-1 U U W U APPLICATIO S I FOR ATIO The serial clock mode is selected on the falling edge of CS. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CS falling edge. Alternatively, CS may be driven HIGH setting SDO to Hi-Z. As described above, CS may be pulled LOW at any time in order to monitor the conversion status. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH.
LTC2415/LTC2415-1 U U W U APPLICATIO S I FOR ATIO 2.7V TO 5.5V VCC 1µF 2 VCC FO = 50Hz REJECTION (LTC2415) = EXTERNAL OSCILLATOR = 60Hz REJECTION (LTC2415) = 50Hz/60Hz REJECTION (LTC2415-1) 14 LTC2415/ LTC2415-1 REFERENCE VOLTAGE 0.1V TO VCC 3 REF + 4 – ANALOG INPUT RANGE –0.5VREF TO 0.
LTC2415/LTC2415-1 U U W U APPLICATIO S I FOR ATIO 2.7V TO 5.5V VCC 1µF 2 VCC FO = 50Hz REJECTION (LTC2415) = EXTERNAL OSCILLATOR = 60Hz REJECTION (LTC2415) = 50Hz/60Hz REJECTION (LTC2415-1) 14 LTC2415/ LTC2415-1 REFERENCE VOLTAGE 0.1V TO VCC 3 REF + 4 REF – ANALOG INPUT RANGE –0.5VREF TO 0.
LTC2415/LTC2415-1 U U W U APPLICATIO S I FOR ATIO by an external oscillator of (LTC2415-1) frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled HIGH before time tEOCtest, the device remains in the sleep state. The conversion result is held in the internal static shift register. new conversion. This is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion.
LTC2415/LTC2415-1 U U W U APPLICATIO S I FOR ATIO weak pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven LOW (if SCK is loaded such that the internal pull-up cannot pull the pin HIGH, the external SCK mode will be selected). A similar situation may occur during the sleep state when CS is pulsed HIGH-LOW-HIGH in order to test the conversion status.
LTC2415/LTC2415-1 U W U U APPLICATIO S I FOR ATIO Internal Serial Clock, Autostart Conversion conversion is immediately started. This is useful in applications requiring periodic monitoring and ultralow power. Figure 17 shows the average supply current as a function of capacitance on CS. This timing mode is identical to the internal serial clock, 2-wire I/O described above with one additional feature. Instead of grounding CS, an external timing capacitor is tied to CS.
LTC2415/LTC2415-1 U U W U APPLICATIO S I FOR ATIO 7 6 tSAMPLE (SEC) 5 4 3 2 VCC = 5V 1 VCC = 3V 0 1 10 100 1000 10000 CAPACITANCE ON CS (pF) 100000 2415 F15 66.6ms and the conversion time of the LTC2413 is 146ms, while the LTC2415-1 is 73ms. In systems where the SDO pin is monitored for the end-of-conversion signal (SDO goes low once the conversion is complete) these two devices can be interchanged.
LTC2415/LTC2415-1 U W U U APPLICATIO S I FOR ATIO LTC2415-1 pins may severely disturb the analog to digital conversion process. Undershoot and overshoot can occur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to LTC2415/LTC2415-1. For reference, on a regular FR-4 board, signal propagation velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces.
LTC2415/LTC2415-1 U U W U APPLICATIO S I FOR ATIO IREF+ − VREFCM ( )AVG = VIN + V0INCM .5 • REQ −V + V −V = IN INCM REFCM I(IN− ) AVG 0.5 • REQ VCC I IN+ RSW (TYP) 20k ILEAK VREF+ ILEAK VCC IIN+ ILEAK RSW (TYP) 20k VCC RSW (TYP) 20k ILEAK VCC ILEAK ( + VREFCM IN + )AVG = −1.5 • VREF0.
LTC2415/LTC2415-1 U W U U APPLICATIO S I FOR ATIO For relatively small values of input capacitance (CIN < 0.01µF), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CIN will deteriorate the converter offset and gain performance without significant benefits of signal filtering and the user is advised to avoid them.
LTC2415/LTC2415-1 U U W U APPLICATIO S I FOR ATIO used for the external source impedance seen by IN+ and IN–, the expected drift of the dynamic current, offset and gain errors will be insignificant (about 1% of their respective values over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient. In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current.
LTC2415/LTC2415-1 U U W U APPLICATIO S I FOR ATIO Reference Current filtering and the user is advised to avoid them. In a similar fashion, the LTC2415/LTC2415-1 sample the differential reference pins REF+ and REF– transferring small amount of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance.
LTC2415/LTC2415-1 U W U U APPLICATIO S I FOR ATIO tance is 1.43MΩ. When FO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential reference resistance is 0.20 • 1012/fEOSCΩ and each ohm of source resistance driving REF + or REF – will result in 2.47 • 10–6 • fEOSCppm gain error. The effect of the source resistance on the two reference pins is additive with respect to this gain error.
LTC2415/LTC2415-1 U U W U APPLICATIO S I FOR ATIO running average can be performed. By averaging two consecutive ADC readings, a Sinc1 notch is combined with the Sinc4 digital filter yielding the frequency response shown in Figures 33 and 34.
LTC2415/LTC2415-1 U W U U APPLICATIO S I FOR ATIO Sample Driver for LTC2415/LTC2415-1 SPI Interface The code begins by declaring variables and allocating four memory locations to store the 32-bit conversion result. This is followed by initializing PORT D’s SPI configuration. The program then enters the main sequence. It activates the LTC2415/LTC2415-1 serial interface by setting the SS output low, sending a logic low to CS.
LTC2415/LTC2415-1 U W U U APPLICATIO S I FOR ATIO Correlated Double Sampling with the LTC2415/LTC2415-1 Figure 37 shows the LTC2415/LTC2415-1 in a correlated double sampling circuit that achieves a noise floor of under 100nV. In this scheme, the polarity of the bridge is alternated every other sample and the result is the average of a pair of samples of opposite sign.
LTC2415/LTC2415-1 U U W U APPLICATIO S I FOR ATIO 10V ELIMINATE FOR 5V OPERATION (CONNECT 2.7k RESISTORS TO 100Ω RESISTORS) 1.5k 1.5k Q2 100Ω DIFFERENCE AMP 10V 0.1µf Q3 3 100Ω R2 27k 22Ω 5V Q4 22Ω 5V 7 U1 LT1219 – 1k Q5 1000pF 2.7k 2 + 5k 6 5 4 C1 0.1µF SHDN 5V R4 499Ω R3 10k 2.7k 5 C3 2.2nF C4 2.2nF 350Ω ×4 R5 499Ω 6 IN– LTC2415/ LTC2415-1 3 REF+ R6 10k 1000pF 10V POL 0.1µf 1k 74HC04 2 Q1 3 22Ω – + R1 61.9Ω 0.1% 5k 6 REF– GND 5 C2 0.
LTC2415/LTC2415-1 U TYPICAL APPLICATIO S ************************************************************ * This example program transfers the LTC2415/LTC2415-1 32-bit output * * conversion result into four consecutive 8-bit memory locations.
LTC2415/LTC2415-1 U TYPICAL APPLICATIO S ******************************************** * The next short loop waits for the * * LTC2415/LTC2415-1’s conversion to finish before * * starting the SPI data transfer * ******************************************** * CONVEND LDAA PORTD Retrieve the contents of port D ANDA #%00000100 Look at bit 2 * Bit 2 = Hi; the LTC2415/LTC2415-1’s conversion is not * complete * Bit 2 = Lo; the LTC2415/LTC2415-1’s conversion is complete BNE CONVEND Branch to the loop’s beginning w
LTC2415/LTC2415-1 U TYPICAL APPLICATIO S Figure 39. Display Graphic U W PCB LAYOUT A D FIL LTC2415CGN Differential Input 24-Bit ADC with 2× Output Rate Demo Circuit DC382 www.linear-tech.
LTC2415/LTC2415-1 U W PCB LAYOUT A D FIL Bottom Layer U PACKAGE DESCRIPTIO GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) 0.189 – 0.196* (4.801 – 4.978) 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0.007 – 0.0098 (0.178 – 0.249) 0.053 – 0.068 (1.351 – 1.727) 0.004 – 0.0098 (0.102 – 0.249) 16 15 14 13 12 11 10 9 0.009 (0.229) REF 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) 0.008 – 0.012 (0.203 – 0.305) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.
LTC2415/LTC2415-1 U TYPICAL APPLICATIO VCC U1 LT1460ACN8-2.5 JP1 JUMPER 1 3 6 VOUT 2 + VIN VCC 2 GND C1 10µF 35V R2 3Ω + U2 LT1236ACN8-5 JP2 JUMPER 1 2 6 VOUT + C2 22µF 25V 4 C3 10µF 35V 10 J3 VCC 1 J5 GND 1 C6 0.
