LTC2413 24-Bit No Latency ∆ΣTM ADC, with Simultaneous 50Hz/60Hz Rejection U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Simultaneous 50Hz/60Hz Rejection (87dB Minimum) Differential Input and Differential Reference with GND to VCC Common Mode Range 2ppm INL and No Missing Codes at 24 Bits 0.1ppm Offset and 2.5ppm Full-Scale Error 0.16ppm Noise No Latency: Digital Filter Settles in a Single Cycle.
LTC2413 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Notes 1, 2) Supply Voltage (VCC) to GND .......................– 0.3V to 7V Analog Input Pins Voltage to GND .................................... – 0.3V to (VCC + 0.3V) Reference Input Pins Voltage to GND .................................... – 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2413C ...........
LTC2413 U CO VERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) PARAMETER CONDITIONS Input Common Mode Rejection DC 2.
LTC2413 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN VIH High Level Input Voltage CS, FO 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 3.3V ● VIL Low Level Input Voltage CS, FO 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V ● VIH High Level Input Voltage SCK 2.7V ≤ VCC ≤ 5.5V (Note 8) 2.7V ≤ VCC ≤ 3.3V (Note 8) ● VIL Low Level Input Voltage SCK 4.
LTC2413 UW TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN MAX UNITS fEOSC External Oscillator Frequency Range ● tHEO External Oscillator High Period ● 2.56 2000 kHz 0.25 390 µs tLEO External Oscillator Low Period ● 0.
LTC2413 U W TYPICAL PERFOR A CE CHARACTERISTICS Total Unadjusted Error vs Temperature (VCC = 5V, VREF = 5V) Total Unadjusted Error vs Temperature (VCC = 5V, VREF = 2.5V) 1.5 1.0 TUE (ppm OF VREF) 0.5 0 –1.0 VCC = 5V REF + = 5V REF – = GND VREF = 5V VINCM = 2.5V FO = GND TA = 90°C 0 TA = –45°C TA = 90°C TA = 25°C –0.5 TA = 25°C TA = –45°C 1 1.5 2 –1.5 2.5 –0.5 0 VIN (V) 0.5 8 1.0 0 INL ERROR (ppm OF VREF) INL ERROR (ppm OF VREF) 10 TA = –45°C TA = 25°C TA = 90°C –0.5 –1.0 1.
LTC2413 U W TYPICAL PERFOR A CE CHARACTERISTICS 8 6 4 GAUSSIAN DISTRIBUTION m = 0.033ppm σ = 0.293ppm 12 2 10 8 6 4 10,000 CONSECUTIVE READINGS VCC = 5V VREF = 2.5V VIN = 0V REF + = 2.5V REF – = GND IN + = 1.25V IN – = 1.25V FO = 460800Hz TA = 25°C GAUSSIAN DISTRIBUTION m = 0.014ppm σ = 0.292ppm 2 0 –1.6 –0.8 0 0.8 OUTPUT CODE (ppm OF VREF) 0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 OUTPUT CODE (ppm OF VREF) 1.6 8 6 4 6 4 GAUSSIAN DISTRIBUTION m = 0.079ppm σ = 0.
LTC2413 U W TYPICAL PERFOR A CE CHARACTERISTICS RMS Noise vs VINCM RMS Noise vs Temperature (TA) 850 825 800 800 775 VCC = 5V REF + = 5V REF – = GND VREF = 5V IN + = VINCM IN – = VINCM VIN = 0V FO = GND TA = 25°C 750 725 700 675 650 –0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VINCM (V) 850 VCC = 5V REF + = 5V REF – = GND IN + = 2.5V IN – = 2.5V VIN = 0V FO = GND 775 800 750 725 675 –25 0 25 50 TEMPERATURE (°C) 75 725 700 675 0 0.5 1 1.5 2 2.5 3 VREF (V) 3.5 4 4.5 0.3 0.3 0.2 0.2 0.
LTC2413 U W TYPICAL PERFOR A CE CHARACTERISTICS + Full-Scale Error vs VCC 2 1 0 REF + = 2.5V REF – = GND VREF = 2.5V IN + = 1.25V IN – = GND FO = GND TA = 25°C –1 –2 –3 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 2 1 0 VCC = 5V REF + = VREF REF – = GND IN + = 0.5 • REF + IN – = GND FO = GND TA = 25°C –1 –2 –3 5.5 3 0 0.5 1 1.5 2 2.5 3 VREF (V) 3.5 4 2413 G28 –1 –2 –3 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 2 1 –60 –100 –2 –120 0 0.5 1 1.5 2 2.5 3 VREF (V) 3.5 4 4.5 –140 0.
LTC2413 U W TYPICAL PERFOR A CE CHARACTERISTICS SUPPLY CURRENT (µA) 210 FO = GND CS = GND SCK = NC SDO = NC 1100 900 VCC = 5.5V 200 190 VCC = 4.1V 180 VCC = 2.7V 800 700 600 500 22 400 21 20 VCC = 5.5V VCC = 4.1V 19 VCC = 2.
LTC2413 W FU CTIO AL BLOCK DIAGRA U U INTERNAL OSCILLATOR VCC GND IN + IN – AUTOCALIBRATION AND CONTROL + –∫ ∫ FO (INT/EXT) ∫ ∑ SDO SERIAL INTERFACE ADC SCK CS REF + – DECIMATING FIR REF – + DAC 2413 FD Figure 1. Functional Block Diagram TEST CIRCUITS VCC 1.69k SDO SDO 1.
LTC2413 U W U U APPLICATIO S I FOR ATIO Once CS is pulled LOW, the device begins outputting the conversion result. There is no latency in the conversion result. The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK (see Figure 3).
LTC2413 U W U U APPLICATIO S I FOR ATIO Input Voltage Range The analog input is truly differential with an absolute/ common mode range for the IN+ and IN– input pins extending from GND – 0.3V to VCC + 0.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2413 converts the bipolar differential input signal, VIN = IN+ – IN–, from – FS = – 0.5 • VREF to +FS = 0.5 • VREF where VREF = REF+ – REF–.
LTC2413 U W U U APPLICATIO S I FOR ATIO on the rising edge of the 32nd SCK pulse. On the falling edge of the 32nd SCK pulse, SDO goes HIGH indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 31) for the next conversion cycle. Table 2 summarizes the output data format. As long as the voltage on the IN+ and IN– pins is maintained within the – 0.3V to (VCC + 0.
LTC2413 U W U U APPLICATIO S I FOR ATIO –80 NORMAL MODE REECTION RATIO (dB) While operating with an external conversion clock of a frequency fEOSC, the LTC2413 provides better than 110dB normal mode rejection in a frequency range fEOSC/2560 ±4%. The normal mode rejection as a function of the input frequency deviation from fEOSC/2560 is shown in Figure 5.
LTC2413 U W U U APPLICATIO S I FOR ATIO Serial Clock Input/Output (SCK) The serial clock signal present on SCK (Pin 13) is used to synchronize the data transfer. Each bit of data is shifted out the SDO pin on the falling edge of the serial clock. In the Internal SCK mode of operation, the SCK pin is an output and the LTC2413 creates its own serial clock by dividing the internal conversion clock by 8. In the External SCK mode of operation, the SCK pin is used as input.
LTC2413 U U W U APPLICATIO S I FOR ATIO As described above, CS may be pulled LOW at any time in order to monitor the conversion status. The serial clock mode is selected on the falling edge of CS. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CS falling edge. Typically, CS remains LOW during the data output state.
LTC2413 U U W U APPLICATIO S I FOR ATIO 2.7V TO 5.5V 1µF 2 VCC FO = EXTERNAL OSCILLATOR = INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION 14 LTC2413 REFERENCE VOLTAGE 0.1V TO VCC 3 REF + 4 REF – ANALOG INPUT RANGE –0.5VREF TO 0.
LTC2413 U U W U APPLICATIO S I FOR ATIO 2.7V TO 5.5V 1µF 2 VCC FO = EXTERNAL OSCILLATOR = INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION 14 LTC2413 REFERENCE VOLTAGE 0.1V TO VCC 3 REF + 4 REF – ANALOG INPUT RANGE –0.5VREF TO 0.5VREF 5 IN + SDO IN – CS 6 1, 7, 8, 9, 10, 15, 16 SCK 13 2-WIRE I/O 12 11 GND CS BIT 31 SDO BIT 30 EOC BIT 29 BIT 28 SIG MSB BIT 27 BIT 26 BIT 5 BIT 0 LSB24 SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION 2413 F08 Figure 8.
LTC2413 U U W U APPLICATIO S I FOR ATIO then tEOCtest is 3.6/fEOSC. If CS is pulled HIGH before time tEOCtest, the device remains in the sleep state. The conversion result is held in the internal static shift register. new conversion. This is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion.
LTC2413 U U W U APPLICATIO S I FOR ATIO weak pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven LOW (if SCK is loaded such that the internal pull-up cannot pull the pin HIGH, the external SCK mode will be selected). A similar situation may occur during the sleep state when CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0), SCK will go LOW.
LTC2413 U U W U APPLICATIO S I FOR ATIO Internal Serial Clock, Autostart Conversion used to shift the conversion result into external circuitry. After the 32nd rising edge, CS is pulled HIGH and a new conversion is immediately started. This is useful in applications requiring periodic monitoring and ultralow power. Figure 15 shows the average supply current as a function of capacitance on CS.
LTC2413 U W U U APPLICATIO S I FOR ATIO 7 CS is discharging; therefore, the internal serial clock timing mode is automatically selected if SCK is floating. It is important to ensure there are no external drivers pulling SCK LOW while CS is discharging. 6 tSAMPLE (SEC) 5 4 3 PRESERVING THE CONVERTER ACCURACY 2 VCC = 5V 1 VCC = 3V 0 1 10 100 1000 10000 CAPACITANCE ON CS (pF) 100000 2413 F13 Figure 13.
LTC2413 U W U U APPLICATIO S I FOR ATIO velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. Thus, a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. This problem becomes particularly difficult when shared control lines are used and multiple reflections may occur.
LTC2413 U U W U APPLICATIO S I FOR ATIO IREF+ VCC RSW (TYP) 20k ILEAK − VREFCM ( )AVG = VIN + V0INCM .5 • REQ −V + VINCM − VREFCM = IN I(IN− ) AVG 0.5 • REQ I IN+ VREF+ ILEAK VCC IIN+ ILEAK VIN+ CEQ 18pF (TYP) ILEAK VCC IIN – ( + VREFCM IN + )AVG = −1.5 • VREF0.−5 •VINCM REQ VREF • REQ I REF − V2 where: ILEAK REF + + REF − VREFCM = 2 VCC VIN = IN+ − IN− VIN – IREF – + VREFCM IN − )AVG = 1.5 • VREF0−.
LTC2413 U W U U APPLICATIO S I FOR ATIO For relatively small values of input capacitance (CIN < 0.01µF), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CIN will deteriorate the converter offset and gain performance without significant benefits of signal filtering and the user is advised to avoid them.
LTC2413 U U W U APPLICATIO S I FOR ATIO +FS ERROR (ppm OF VREF) 300 Reference Current VCC = 5V REF + = 5V REF – = GND IN + = 3.75V IN – = 1.25V FO = GND TA = 25°C 240 180 In a similar fashion, the LTC2413 samples the differential reference pins REF+ and REF– transfering small amount of charge to and from the external driving circuits, thus produces a dynamic reference current. This current does not change the converter offset but it may degrade the gain and INL performance.
LTC2413 U U W U APPLICATIO S I FOR ATIO Figure␣ 27 shows the typical INL error due to the source resistance driving the REF+ or REF– pins when large CREF values are used. The effect of the source resistance on the two reference pins is additive with respect to this INL error. In general, matching of source impedance for the REF+ and REF– pins does not help the gain or the INL error.
LTC2413 U W U U APPLICATIO S I FOR ATIO 15 12 RSOURCE = 1000Ω INL (ppm OF VREF) 9 RSOURCE = 500Ω 6 3 0 –3 RSOURCE = 100Ω –6 –9 –12 –15 –0.5 –0.4–0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5 VINDIF/VREFDIF VCC = 5V FO = GND REF+ = 5V CREF = 10µF TA = 25°C REF– = GND 2413 F27 VINCM = 0.5 • (IN + + IN –) = 2.5V Figure 27.
LTC2413 U W U U APPLICATIO S I FOR ATIO Third, an increase in the frequency of the external oscillator above 460800Hz (a more than 3× increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. This will result in a progressive degradation in the converter accuracy and linearity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Fig- ures␣ 28 through 35, inclusive.
LTC2413 U U W U APPLICATIO S I FOR ATIO 24 22 RESOLUTION = LOG2(VREF/INLMAX) 23 20 TA = 25°C 21 20 TA = 85°C 19 18 VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V VIN = 0V FO = EXTERNAL OSCILLATOR RESOLUTION = LOG2(VREF/NOISERMS) 17 16 15 14 13 12 RESOLUTION (BITS) RESOLUTION (BITS) 22 0 18 TA = 85°C TA = 25°C 16 14 VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V –2.5V < VIN < 2.
LTC2413 U W U U APPLICATIO S I FOR ATIO Input Bandwidth The combined effect of the internal sinc4 digital filter and of the analog and digital autocalibration circuits determines the LTC2413 input bandwidth. When the internal oscillator is used (FO = LOW), the 3dB input bandwidth is 3.3Hz. If an external conversion clock generator of frequency fEOSC is connected to the FO pin, the 3dB input bandwidth is 0.236 • 10–6 • fEOSC.
LTC2413 U W U U APPLICATIO S I FOR ATIO Normal Mode Rejection and Antialiasing One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2413 significantly simplifies antialiasing filter requirements. The sinc4 digital filter provides greater than 120dB normal mode rejection at all frequencies except DC and integer multiples of the modulator sampling frequency (fS).
LTC2413 U U W U APPLICATIO S I FOR ATIO The user can expect to achieve in practice this level of performance using the internal oscillator, as it is demonstrated by Figure 41. Typical measured values of the normal mode rejection of the LTC2413 operating with the internal oscillator are shown in Figure 41 superimposed over the theoretical calculated curve. As a result of these remarkable normal mode specifications, minimal (if any) antialias filtering is required in front of the LTC2413.
LTC2413 U U W U APPLICATIO S I FOR ATIO range of 5V peak-to-peak. Figure 42 shows measurement results for the LTC2413 normal mode rejection ratio with a 7.5V peak-to-peak (150% of full scale) input signal superimposed over the more traditional normal mode rejection ratio results obtained with a 5V peak-to-peak (full scale) input signal. It is clear that the LTC2413 rejection performance is maintained with no compromises in this extreme situation.
LTC2413 U W U U APPLICATIO S I FOR ATIO For those applications that cannot be fulfilled by the LTC2413 alone, compensating for error in external amplification can be done effectively due to the “no latency” feature of the LTC2413. No latency operation allows samples of the amplifier offset and gain to be interleaved with weighing measurements. The use of correlated double sampling allows suppression of 1/f noise, offset and thermocouple effects within the bridge.
LTC2413 U W U U APPLICATIO S I FOR ATIO has common mode rejection far beyond that of most amplifiers. The LTC1051 is a dual autozero amplifier that can be used to produce a gain of 15 before its input referred noise dominates the LTC2413 noise. This example shows a gain of 34, that is determined by a feedback network built using a resistor array containing 8 individual resistors. The resistors are organized to optimize temperature tracking in the presence of thermal gradients.
LTC2413 U U W U APPLICATIO S I FOR ATIO The basic circuit shown in Figure 46 shows connections for a full 4-wire connection to the sensor, which may be located remotely. The differential input connections will reject induced or coupled 60Hz interference, however, the reference inputs do not have the same rejection. If 60Hz or other noise is present on the reference input, a low pass filter is recommended as shown in Figure 47.
LTC2413 U U W U APPLICATIO S I FOR ATIO The circuits in Figures 48 and 50 could be used where multiple bridge circuits are involved and bridge output can be multiplexed onto a single LTC2413, via an inexpensive multiplexer such as the 74HC4052. be a source of error. The fact that input offset voltage has relatively little effect on overall error may lead one to use low performance amplifiers for this application.
LTC2413 U W U U APPLICATIO S I FOR ATIO VS 2.7V TO 5.5V 2 R1 25.5k 0.1% 3 REF + 4 REF – 5 IN + 6 IN – VCC LTC2413 PLATINUM 100Ω RTD GND 1, 7, 8, 9, 10, 15, 16 2413 F46 Figure 46. Remote Half Bridge Interface 5V R2 10k 0.1% R1 10k, 5% 5V R3 10k 5% + 1µF 2 560Ω LTC1050 3 REF + 4 REF – VCC – LTC2413 PLATINUM 100Ω RTD 10k 5 IN + 10k 6 IN – GND 1, 7, 8, 9, 10, 15, 16 2413 F47 Figure 47.
LTC2413 U U W U APPLICATIO S I FOR ATIO 15V 15V U1 4 LTC1043 15V 7 20Ω Q1 2N3904 6 + 4 200Ω 2 LT1236-5 + 10V + 47µF 11 0.1µF 12 14 13 + 10µF 0.1µF 1k 5V 7 1µF –15V 33Ω 8 * LTC1150 – 10V 3 17 350Ω BRIDGE 5V 0.1µF 2 VCC LTC2413 33Ω 7 6 + 3 4 –15V 5 IN + 6 IN – – 1, 7, 8, 9, 10, 15, 16 6 * 2 2 3 –15V 1k REF – GND 5 LTC1150 20Ω REF + 4 U2 LTC1043 15V Q2 2N3906 3 15 18 0.
LTC2413 U W U U APPLICATIO S I FOR ATIO 5V 5V + 16 47µF 12 14 15 11 3 REF + 4 REF – 2 VCC LTC2413 74HC4052 1 5 TO OTHER DEVICES 13 5 IN + 3 6 IN – 2 6 4 8 9 10 GND 1, 7, 8, 9, 10, 15, 16 A0 A1 2413 F49 Figure 49.
LTC2413 U PACKAGE DESCRIPTIO GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) TOP VIEW GND 1 16 GND VCC 2 15 GND REF + 3 14 FO REF – 4 13 SCK IN + 5 12 SDO IN – 6 11 CS GND 7 10 GND GND 8 9 GND GN PACKAGE 16-LEAD PLASTIC SSOP sn2413 2413fs Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
LTC2413 U TYPICAL APPLICATIO 15V + 20Ω Q1 2N3904 1/2 LT1112 1 – C1 0.1µF 22Ω 5V 3 LT1236-5 + C3 47µF 2 C1 0.1µF RN1 10k 10V 1 5V 2 3 4 350Ω BRIDGE TWO ELEMENTS VARYING 2 RN1 10k VCC LTC2413 –5V 8 RN1 10k 5 7 6 C2 0.1µF 33Ω ×2 Q2, Q3 2N3906 ×2 RN1 10k 20Ω 7 REF + 4 REF – 5 IN + 6 IN – GND 1, 7, 8, 9, 10, 15, 16 15V RN1 IS CADDOCK T914 10K-010-02 8 – 1/2 LT1112 4 –15V 3 + 6 5 –15V 2413 F50 Figure 50.
