Datasheet

LTC2411/LTC2411-1
20
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2411/LTC2411-1’s inter-
nal pull-up at pin SCK is disabled. Normally, SCK is not
externally driven if the device is in the internal SCK timing
mode. However, certain applications may require an ex-
ternal driver on SCK. If this driver goes Hi-Z after output-
ting a LOW signal, the LTC2411/LTC2411-1’s internal
pull-up remains disabled. Hence, SCK remains LOW. On
the next falling edge of CS, the device is switched to the
external SCK timing mode. By adding an external 10k pull-
up resistor to SCK, this pin goes HIGH once the external
driver goes Hi-Z. On the next CS falling edge, the device
will remain in the internal SCK timing mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as t
EOCtest
), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier.
Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
SDO
SCK
(INTERNAL)
CS
LSB
24
MSBSIG
BIT 5 BIT 0BIT 27 BIT 26BIT 28BIT 29BIT 30
EOC
BIT 31
SLEEP
DATA OUTPUT CONVERSIONCONVERSION
2411 F10
V
CC
F
O
REF
+
REF
–
SCK
IN
+
IN
–
SDO
GND
CS
110
2
3
9
4
5
8
6
7
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
1µF
2.7V TO 5.5V
2-WIRE I/O
= 50Hz REJECTION (LTC2411)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2411)
= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)
V
CC
LTC2411/
LTC2411-1
APPLICATIO S I FOR ATIO
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