Datasheet

LTC2411/LTC2411-1
18
Figure 7. External Serial Clock, CS = 0 Operation
EOC
BIT 31
SDO
SCK
(EXTERNAL)
CS
MSBSIG
BIT 0
LSB
24
BIT 5BIT 27 BIT 26BIT 28BIT 29BIT 30
SLEEP DATA OUTPUT CONVERSION
2411 F07
CONVERSION
V
CC
F
O
REF
+
REF
–
SCK
IN
+
IN
–
SDO
GND
CS
110
2
3
9
4
5
8
6
7
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
2-WIRE I/O
1µF
2.7V TO 5.5V
= 50Hz REJECTION (LTC2411)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2411)
= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)
V
CC
LTC2411/
LTC2411-1
Figure 8. Internal Serial Clock, Single Cycle Operation
Data is shifted out the SDO pin on each falling edge of SCK
enabling external circuitry to latch data on the rising edge
of SCK. EOC can be latched on the first rising edge of SCK.
On the 32nd falling edge of SCK, SDO goes HIGH (EOC␣ =␣ 1)
indicating a new conversion has begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
SDO
SCK
(INTERNAL)
CS
MSBSIG
BIT 0
LSB
24
BIT 5
TEST EOC
BIT 27 BIT 26BIT 28BIT 29BIT 30
EOC
BIT 31
SLEEP DATA OUTPUT CONVERSIONCONVERSION
2411 F08
<t
EOCtest
V
CC
10k
Hi-Z Hi-Z Hi-Z Hi-Z
TEST EOC
V
CC
F
O
REF
+
REF
–
SCK
IN
+
IN
–
SDO
GND
CS
110
2
3
9
4
5
8
6
7
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
3-WIRE
SPI INTERFACE
1µF
2.7V TO 5.5V
= 50Hz REJECTION (LTC2411)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2411)
= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)
V
CC
LTC2411/
LTC2411-1
APPLICATIO S I FOR ATIO
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