Datasheet

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LTC2411/LTC2411-1

The LTC

2411/LTC2411-1 are 2.7V to 5.5V micropower

24-bit differential ∆Σ analog-to-digital converters with an

integrated oscillator, 2ppm INL and 0.29ppm RMS noise.

They use delta-sigma technology and provide single cycle

settling time for multiplexed applications. Through a

single pin, the LTC2411 can be configured for better than

110dB differential mode rejection at 50Hz or 60Hz ±2%,

and the LTC2411-1 can provide better than 87dB input

differential mode rejection over the range of 49Hz to

61.2Hz, or they can be driven by an external oscillator for

a user-defined rejection frequency. The LTC2411 and

LTC2411-1 are identical when driven by an external

oscillator. The internal oscillator requires no external

frequency setting components.

The converters accept any external differential reference

voltage from 0.1V to V

for flexible ratiometric and

remote sensing measurement configurations. The full-

scale differential input range is from –0.5V

REF

to 0.5V

REF

The reference common mode voltage, V

REFCM

, and the

input common mode voltage, V

INCM

, may be indepen-

dently set anywhere within the GND to V

range of the

LTC2411/LTC2411-1. The DC common mode input rejec-

tion is better than 140dB.

The LTC2411/LTC2411-1 communicate through a flexible

3-wire digital interface that is compatible with SPI and

MICROWIRE

protocols.

■

Direct Sensor Digitizer

■

Weight Scales

■

Direct Temperature Measurement

■

Gas Analyzers

■

Strain Gauge Transducers

■

Instrumentation

■

Data Acquisition

■

Industrial Process Control

■

6-Digit DVMs

, LTC and LT are registered trademarks of Linear Technology Corporation.

■

24-Bit ADC in an MS10 Package

■

Low Supply Current (200µA in Conversion Mode

and 4µA in Autosleep Mode)

■

Differential Input and Differential Reference

with GND to V

Common Mode Range

■

2ppm INL, No Missing Codes

■

4ppm Full-Scale Error and 1ppm Offset

■

0.29ppm Noise

■

No Latency: Digital Filter Settles in a Single Cycle.

Each Conversion Is Accurate, Even After an

Input Step

■

Single Supply 2.7V to 5.5V Operation

■

Internal Oscillator—No External Components

Required

■

110dB Min, Pin Selectable 50Hz/60Hz Notch Filter

(LTC2411)

■

Simultaneous 50Hz/60Hz Rejection (LTC2411-1)

24-Bit No Latency ∆Σ

ADC

with Differential Input and

Reference in MSOP

No Latency ∆Σ is a trademark of Linear Technology Corporation.

MICROWIRE is a trademark of National Semiconductor Corporation.

DESCRIPTIO

FEATURES

APPLICATIO S

TYPICAL APPLICATIO

REF

–

SCK

–

SDO

GND

110

REFERENCE

VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

–0.5V

REF

TO 0.5V

REF

= INTERNAL OSC/50Hz REJECTION (LTC2411)

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/60Hz REJECTION (LTC2411)

= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)

3-WIRE

SPI INTERFACE

1µF

2.7V TO 5.5V

LTC2411/

LTC2411-1

2411 TA01

LTC2411/

LTC2411-1

REF

–

GND F

–

1µF

SCK

3-WIRE

SPI

INTERFACE

SDO

2411 TA02

610

BRIDGE

IMPEDANCE

100Ω TO 10kΩ

Summary of content (40 pages)

PAGE 1
LTC2411/LTC2411-1 24-Bit No Latency ∆ΣTM ADC with Differential Input and Reference in MSOP DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 24-Bit ADC in an MS10 Package Low Supply Current (200µA in Conversion Mode and 4µA in Autosleep Mode) Differential Input and Differential Reference with GND to VCC Common Mode Range 2ppm INL, No Missing Codes 4ppm Full-Scale Error and 1ppm Offset 0.29ppm Noise No Latency: Digital Filter Settles in a Single Cycle.
PAGE 2
LTC2411/LTC2411-1 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Notes 1, 2) Supply Voltage (VCC) to GND .......................– 0.3V to 7V Analog Input Pins Voltage to GND .................................... – 0.3V to (VCC + 0.3V) Reference Input Pins Voltage to GND .................................... – 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2411C .
PAGE 3
LTC2411/LTC2411-1 U CO VERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) PARAMETER CONDITIONS Input Common Mode Rejection DC 2.5V ≤ REF + ≤ V – CC, REF = GND, – + IN = IN ≤ 5V MIN TYP ● 130 140 Input Common Mode Rejection 60Hz ±2% (LTC2411) 2.5V ≤ REF+ ≤ VCC, REF – = GND, GND ≤ IN – = IN + ≤ 5V, (Note 7) ● 140 dB Input Common Mode Rejection 50Hz ±2% (LTC2411) 2.
PAGE 4
LTC2411/LTC2411-1 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage CS, FO 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 3.3V ● MIN VIL Low Level Input Voltage CS, FO 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V ● VIH High Level Input Voltage SCK 2.7V ≤ VCC ≤ 5.5V (Note 9) 2.7V ≤ VCC ≤ 3.
PAGE 5
LTC2411/LTC2411-1 WU TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 6
LTC2411/LTC2411-1 U W TYPICAL PERFOR A CE CHARACTERISTICS Total Unadjusted Error (VCC = 5V, VREF = 5V) Total Unadjusted Error (VCC = 5V, VREF = 2.5V) 3 1.5 2 1.0 Total Unadjusted Error (VCC = 2.7V, VREF = 2.5V) 10 1 TA = 25°C 0 –2 TA = –45°C TA = –45°C 0 –0.5 VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V FO = GND VCC = 5V REF + = 2.5V REF – = GND VINCM = 2.5V FO = GND –1.0 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 VIN (V) 1 1.5 2 2.5 –1.5 –1.25 –0.75 TA = 90°C –0.25 0.25 VIN (V) 0.
PAGE 7
LTC2411/LTC2411-1 U W TYPICAL PERFOR A CE CHARACTERISTICS RMS Noise vs Temperature 1.60 VCC = 5V VIN = 0V REF + = 5V FO = GND – REF = GND TA = 25°C VCC = 5V VREF = 5V VIN = 0V VINCM = GND FO = GND 1.55 1.50 RMS NOISE (µV) RMS NOISE (µV) 1.55 1.45 1.40 1.50 1.55 1.45 1.40 1.35 1.35 1.30 –1 0 1 3 2 VINCM (V) 5 4 1.30 –45 –30 –15 6 0 15 30 45 60 TEMPERATURE (°C) 75 1.35 1.30 VCC = 5V REF + = 5V REF – = GND VIN = 0V FO = GND TA = 25°C –0.2 –0.3 –0.4 –0.1 –0.5 –0.6 –0.7 –0.
PAGE 8
LTC2411/LTC2411-1 U W TYPICAL PERFOR A CE CHARACTERISTICS + Full-Scale Error vs Temperature –Full-Scale Error vs Temperature 2 1 0 –1 –2 –3 –4 –5 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 2 1 0 VCC = 5V REF + = 5V REF – = GND + –2 IN – = GND IN = 2.5V FO = GND –3 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) –1 2411 G19 –40 –80 1 0 –1 –2 –3 –4 0 –60 –20 –40 –80 –60 –120 –120 –120 –140 10k 100k 1k 100 FREQUENCY AT VCC (Hz) 0 1M 30 0 0 REJECTION (dB) REJECTION (dB) VCC = 4.
PAGE 9
LTC2411/LTC2411-1 U W TYPICAL PERFOR A CE CHARACTERISTICS Conversion Current vs Temperature 650 VCC = 5.5V SUPPLY CURRENT (µA) 210 VCC = 5V 200 190 VCC = 3V 180 REF + = VCC 600 REF – = GND IN + = GND 550 IN – = GND 500 TA = 25°C SCK = NC 450 SDO = NC CS = GND 400 FO = EXT OSC 350 300 75 150 90 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) VCC = 3V –20 VREF = 5V –40 VCC = 5V REF – = GND VINCM = 2.
PAGE 10
LTC2411/LTC2411-1 U U U PI FU CTIO S the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. internal pull-up is automatically activated in Internal Serial Clock Operation mode. The Serial Clock Operation mode is determined by the logic level applied to the SCK pin at power up or during the most recent falling edge of CS. SDO (Pin 8): Three-State Digital Output.
PAGE 11
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO CONVERTER OPERATION Converter Operation Cycle The LTC2411/LTC2411-1 are low power, delta-sigma analog-to-digital converters with an easy-to-use 3-wire serial interface (see Figure 1). Their operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 2).
PAGE 12
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO integrity of the conversion result and of the serial interface mode selection. (See the 2-wire I/O sections in the Serial Interface Timing Modes section.) When the VCC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) signal with a duration of approximately 1ms. The POR signal clears all internal registers.
PAGE 13
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO above +FS. If both Bit 29 and Bit 28 are LOW, the differential input voltage is below –FS. The function of these bits is summarized in Table 1. Table 1. LTC2411/LTC2411-1 Status Bits Bit 31 Bit 30 Bit 29 Bit 28 EOC DMY SIG MSB Input Range VIN ≥ 0.5 • VREF 0 0 1 1 0V ≤ VIN < 0.5 • VREF 0 0 1 0 –0.5 • VREF ≤ VIN < 0V 0 0 0 1 VIN < – 0.5 • VREF 0 0 0 0 Bits 28-5 are the 24-bit conversion result MSB first.
PAGE 14
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO Frequency Rejection Selection (FO) (LTC2411 Only) The LTC2411 internal oscillator provides better than 110dB normal mode rejection at the line frequency and all its harmonics for 50Hz ±2% or 60Hz ±2%. For 60Hz rejection, FO should be connected to GND while for 50Hz rejection the FO pin should be connected to VCC. The selection of 50Hz or 60Hz rejection can also be made by driving FO to an appropriate logic level.
PAGE 15
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO Table 3. LTC2411/LTC2411-1 State Duration State Operating Mode CONVERT Internal Oscillator Duration FO = LOW (LTC2411) (60Hz Rejection) 133ms, Output Data Rate ≤ 7.5 Readings/s FO = HIGH (LTC2411) (50Hz Rejection) 160ms, Output Data Rate ≤ 6.2 Readings/s FO = LOW (LTC2411-1) (Simultaneous 50Hz/60Hz Rejection) 147ms, Output Data Rate ≤ 6.
PAGE 16
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO Table 4.
PAGE 17
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO device automatically enters the low power sleep state once the conversion is complete. requiring all 32 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. When the device is in the sleep state (EOC = 0), its conversion result is held in an internal static shift register. The device remains in the sleep state until the first rising edge of SCK is seen while CS is LOW.
PAGE 18
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO Internal Serial Clock, Single Cycle Operation Data is shifted out the SDO pin on each falling edge of SCK enabling external circuitry to latch data on the rising edge of SCK. EOC can be latched on the first rising edge of SCK. On the 32nd falling edge of SCK, SDO goes HIGH (EOC␣ =␣ 1) indicating a new conversion has begun.
PAGE 19
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO if the device is using its internal oscillator for the LTC2411 (FO = logic LOW or HIGH) and 26µs for the LTC2411-1 (FO = logic LOW). If FO is driven by an external oscillator of frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled HIGH before time tEOCtest, the device remains in the sleep state. The conversion result is held in the internal static shift register.
PAGE 20
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. If CS is pulled HIGH while the converter is driving SCK LOW, the internal pull-up is not available to restore SCK to a logic HIGH state.
PAGE 21
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO The internal serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 1ms after VCC exceeds 1.9V. An internal weak pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven LOW (if SCK is loaded such that the internal pull-up cannot pull the pin HIGH, the external SCK mode will be selected).
PAGE 22
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO Particular attention must be given to the connection of the FO signal when the LTC2411/LTC2411-1 are used with an external conversion clock. This clock is active during the conversion time and the normal mode rejection provided by the internal digital filter is not very high at this frequency. A normal mode signal of this frequency at the converter reference terminals may result into DC gain and INL errors.
PAGE 23
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO a 13µs (14.2µs) sampling period. Thus, for settling errors of less than 1ppm, the driving source impedance should be chosen such that τ ≤ 13µs/14 = 920ns (1.02µs). When an external oscillator of frequency fEOSC is used, the sampling period is 2/fEOSC and, for a settling error of less than 1ppm, τ ≤ 0.14/fEOSC. they include the effect of the actual second order input network together with the nonlinear settling process of the input amplifiers.
PAGE 24
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO Larger values of input capacitors (CIN > 0.01µF) may be required in certain configurations for antialiasing or general input signal filtering. Such capacitors will average the input sampling charge and the external source resistance will see a quasi constant input differential impedance. For the LTC2411, when FO = LOW (internal oscillator and 60Hz notch), the typical differential input resistance is 5.
PAGE 25
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO 50 OFFSET ERROR (ppm OF VREF) 30 B 20 does not change the converter offset, but it may degrade the gain and INL performance. The effect of this current can be analyzed in the same two distinct situations. VCC = 5V REF + = 5V REF – = GND IN + = IN – = VINCM A 40 C 10 D 0 E –10 F –20 –30 FO = GND TA = 25°C RSOURCEIN – = 500Ω CIN = 10µF G –40 –50 0 0.5 1 1.5 2 2.
PAGE 26
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO 50 VCC = 5V REF + = 5V REF – = GND IN + = 3.75V IN – = 1.25V FO = GND TA = 25°C –10 –20 –FS ERROR (ppm OF VREF) +FS ERROR (ppm OF VREF) 0 CREF = 0pF –30 CREF = 100pF CREF = 0.001µF –40 VCC = 5V REF + = 5V REF – = GND 40 IN + = 1.25V IN – = 3.75V FO = GND 30 TA = 25°C CREF = 0pF 20 CREF = 100pF CREF = 0.001µF 10 CREF = 0.01µF CREF = 0.
PAGE 27
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO user is thus advised to minimize the combined source impedance driving the REF+ and REF– pins rather than to try to match it. The magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typical better than 1%.
PAGE 28
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO 250 VCC = 5V VREF = 5V VINCM = 2.5V VIN = 0V FO = EXT OSC 80 40 VCC = 5V VREF = 5V IN + = 3.75V IN – = 1.25V FO = EXT OSC 200 +FS ERROR (ppm OF VREF) OFFSET ERROR (ppm OF VREF) 120 TA = 85°C 0 –40 TA = 25°C 150 100 TA = 85°C 50 TA = 25°C 0 –80 –50 –120 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2411 F21 2411 F20 Figure 20.
PAGE 29
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO 22 22 VREF = 5V 20 VREF = 2.5V 20 VCC = 5V REF – = GND VINCM = 2.5V 19 VIN = 0V FO = EXT OSC RES = LOG2(VREF/NOISERMS) TA = 25°C 18 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) RESOLUTION (BITS) RESOLUTION (BITS) 21 18 VREF = 2.5V VCC = 5V REF – = GND VINCM = 2.5V VIN = 0V FO = EXT OSC RES = LOG2(VREF/INLMAX) TA = 25°C 14 12 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2411 F27 2411 F26 Figure 27.
PAGE 30
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO internal calibration and filtering. The noise of the driving amplifier referred to the converter input and including all these effects can be calculated as N␣ = ni • √freqi. The total system noise (referred to the LTC2411/LTC2411-1 input) can now be obtained by summing as square root of sum of squares the three ADC input referred noise sources: the LTC2411/LTC2411-1 internal noise (1.
PAGE 31
LTC2411/LTC2411-1 U W U U 0 0 –10 –10 INPUT NORMAL MODE REJECTION (dB) INPUT NORMAL MODE REJECTION (dB) APPLICATIO S I FOR ATIO –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (Hz) –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz) 8fN 2411 F33 2411 F32 Figure 32.
PAGE 32
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO NORMAL MODE REJECTION (dB) MEASURED DATA CALCULATED DATA –20 –40 – 60 VCC = 5V VREF = 5V REF – = GND VINCM = 2.5V VIN(P-P) = 5V FO = GND TA = 25°C –80 –100 –120 NORMAL MODE REJECTION (dB) 0 0 VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) –20 –40 VCC = 5V VREF = 5V VINCM = 2.
PAGE 33
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO Another option is the use of a reference within the 5V input range of the LTC2411/LTC2411-1 and developing excitation via fixed gain, or LTC1043 based voltage multiplication, along with remote feedback in the excitation amplifiers, as shown in Figures 45 and 46. Averaging 64 samples however reduces the noise level by a factor of eight, bringing the resolving power to 1 part in 40000, comparable to better weighing systems.
PAGE 34
LTC2411/LTC2411-1 U U W U APPLICATIO S I FOR ATIO the sensor largely eliminates the need for protection devices, RFI suppression and wiring. The LTC2411/ LTC2411-1 exhibit extremely low temperature dependent drift. As a result, exposure to external ambient temperature ranges does not compromise performance. The incorporation of any amplification considerably complicates thermal stability, as input offset voltages and currents, temperature coefficient of gain settling resistors all become factors.
PAGE 35
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO Note that this 4-amplifier topology has advantages over the typical integrated 3-amplifier instrumentation amplifier in that it does not have the high noise level common in the output stage that usually dominates when an instrumentation amplifier is used at low gain. If this amplifier is used at a gain of 10, the gain error is only 10ppm and input referred noise is reduced to 0.15µVRMS.
PAGE 36
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO bridge output can be eliminated completely; if the reference arm of the bridge is used as the reference to the ADC, as shown in Figure 43. The LTC2411/LTC2411-1 can accept inputs up to 1/2 VREF. Hence, the reference resistor R1 must be at least 2× the highest value of the variable resistor. result as the two resistor version, but has a few benefits.
PAGE 37
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO 15V 7 20Ω Q1 2N3904 15V U1 4 LTC1043 15V 6 + 4 200Ω 2 LT1236-5 + 47µF 11 10V + 0.1µF 12 14 13 + 10µF 0.1µF 1k 5V 7 1µF –15V 33Ω 8 * LTC1150 – 10V 3 17 350Ω 10V BRIDGE 5V 0.1µF 1 VCC LTC2411/ LTC2411-1 2 REF + 3 REF – –10V 33Ω Q2 2N3906 6 + 3 4 –15V – 6 6 * 2 2 3 –15V 1k IN – GND 5 LTC1150 20Ω IN + 5 U2 LTC1043 15V 7 4 15 18 0.
PAGE 38
LTC2411/LTC2411-1 U W U U APPLICATIO S I FOR ATIO gain error or due to offset voltages. A 1µV/°C offset voltage drift translates into 0.05ppm/°C gain error. Simpler alternatives, with the amplifiers providing gain using resistor arrays for feedback, can produce results that are similar to bridge sensing schemes via attenuators. Note that the amplifiers must have high open-loop gain or gain error will be a source of error.
PAGE 39
LTC2411/LTC2411-1 U PACKAGE DESCRIPTIO MS10 Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 0.118 ± 0.004* (3.00 ± 0.102) 10 9 8 7 6 0.118 ± 0.004** (3.00 ± 0.102) 0.193 ± 0.006 (4.90 ± 0.15) 1 2 3 4 5 0.034 (0.86) REF 0.043 (1.10) MAX 0.007 (0.18) 0° – 6° TYP 0.021 ± 0.006 (0.53 ± 0.015) SEATING PLANE 0.007 – 0.011 (0.17 – 0.27) 0.0197 (0.50) BSC 0.005 ± 0.002 (0.13 ± 0.05) MSOP (MS10) 1100 * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
PAGE 40
LTC2411/LTC2411-1 U TYPICAL APPLICATIO 15V + 20Ω Q1 2N3904 1/2 LT1112 1 – C1 0.1µF 22Ω 5V 3 LT1236-5 + C3 47µF 2 C1 0.1µF RN1 10k 10V 1 5V 2 RN1 10k 350Ω BRIDGE TWO ELEMENTS VARYING 3 1 VCC LTC2411/ LTC2411-1 2 REF + 3 REF – 4 –5V 8 RN1 10k 5 7 IN + 5 IN – GND 6 6 C2 0.1µF 33Ω ×2 Q2, Q3 2N3906 ×2 RN1 10k 4 20Ω 7 15V RN1 IS CADDOCK T914 10K-010-02 8 4 –15V – 1/2 LT1112 –15V + 6 5 2411 F47 Figure 47.