Datasheet

20
LTC2404/LTC2408
APPLICATIONS INFORMATION
WUU
U
SCKCLK
SDO
D
IN
CSADC
CSMUX
t
EOCtest
MSB
SUB
LSB
SUB
LSB
SUB
LSB
SUB
LSB
EXRSIG
BIT0
LSB
BIT4 BIT3 BIT2 BIT1BIT27BIT26BIT28BIT29BIT30BIT31
24048 F10
TEST EOC
DON’T CARE DON’T CAREEN D2 D1 D0
Hi-Z Hi-ZHi-Z
TEST EOCTEST EOC
V
CC
CS
10k
F
O
V
REF
CSMUX
CSADC
SCK
CLK
MUXOUT
ADCIN
D
IN
GND SDO
0.1V
TO V
CC
CH0
TO CH7
–0.12V
REF
TO 1.12V
REF
2.7V TO 5.5V
LTC2404/LTC2408
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
Figure 10. Internal Serial Clock Timing Diagram
state. The internal serial clock (SCK) generated by the ADC
is applied to the multiplexer clock input (CLK).
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CSADC. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CSADC. An internal weak pull-up
resistor is active on the SCK pin during the falling edge of
CSADC; therefore, the internal serial clock timing mode is
automatically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CSADC
is HIGH. At any time during the conversion cycle, CSADC
may be pulled LOW in order to monitor the state of the
converter. Once CSADC is pulled LOW, SCK goes LOW
and EOC is output to the SDO pin. EOC = 1 while a
conversion is in progress and EOC = 0 if the device is in the
sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CSADC remains LOW. In order to prevent the
device from exiting the low power sleep state, CSADC
must be pulled HIGH before the first rising edge of SCK. In
the internal SCK timing mode, SCK goes HIGH and the
device begins outputting data at time t
EOCtest
after the
falling edge of CSADC (if EOC = 0) or t
EOCtest
after EOC
goes LOW (if CSADC is LOW during the falling edge of
EOC). The value of t
EOCtest
is 23µs if the device is using its
internal oscillator (F
0
= logic LOW or HIGH). If F
O
is driven
by an external oscillator of frequency f
EOSC
, then t
EOCtest
is
3.6/f
EOSC
. If CSADC is pulled HIGH before time t
EOCtest
, the
device remains in the sleep state. The conversion result is
held in the internal static shift register.
If CSADC remains LOW longer than t
EOCtest
, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output