Datasheet

19
LTC2404/LTC2408
APPLICATIONS INFORMATION
WUU
U
Typically, CSADC remains LOW during the data output
state. However, the data output state may be aborted by
pulling CSADC HIGH anytime between the first rising edge
and the 32nd falling edge of SCK, see Figure 9. On the
rising edge of CSADC, the device aborts the data output
state and immediately initiates a new conversion. This is
useful for systems not requiring all 32 bits of output data,
aborting an invalid conversion cycle or synchronizing the
start of a conversion.
Internal Serial Clock
This timing mode uses an internal serial clock to shift out
the conversion result and program the multiplexer, see
Figure 10. A CS signal directly drives the CSADC input,
while the inverse of CS drives the CSMUX input. The CS
signal is used to monitor and control the state of the
conversion cycles as well as enable the channel selection.
The multiplexer is programmed during the data output
Figure 8. Use of Look Ahead to Program Multiplexer After Data Output
SCK/CLK
SDO
CONVERTER
STATE
D
IN
CSADC/
CSMUX
MSB
SUB
LSB
EXRSIG
BIT0
LSB
BIT4BIT27BIT26BIT28BIT29BIT30BIT31
24048 F08
TEST EOC
CONV SLEEP DATA OUTPUT INTERNAL CALIBRATION
66ms LOOK AHEAD
CONVERSION ON SELECTED CHANNEL
DON’T CARE DON’T CAREEN D2 D1 D0
Hi-Z
TEST EOC
66ms CONVERT
133ms CONVERSION CYCLE (OUTPUT RATE = 7.5Hz)
Figure 9. External Serial Clock with Reduced Data Output Length Timing Diagram
SCK/CLK
SDO
D
IN
CSADC/
CSMUX
V
CC
CS
SCK
F
O
V
REF
CSMUX
CSADC
SCK
CLK
MUXOUT
ADCIN
D
IN
GND SDO
0.1V
TO V
CC
CH0
TO CH7
–0.12V
REF
TO 1.12V
REF
2.7V TO 5.5V
LTC2404/LTC2408
MSB
EXRSIG
LSB
BIT8BIT9BIT27 BIT26BIT28BIT29BIT30BIT31
24048 F09
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
TEST EOC
DON’T CARE DON’T CAREEN D2 D1 D0
Hi-ZHi-Z
TEST EOC